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Innovative Memory Test Cell Leverages Scalable Parallelism and Compact Footprint for Final Test

By Zain Abadin, Sr. Director, Device Interface and Handling, and Masahito Kondo, Integrated Test Cell Solution Lead, Advantest

Products ranging from datacenter servers to automobiles require more and faster memory ICs, which must be thoroughly yet cost-effectively tested. As these chips evolve to provide ever higher levels of performance and quality, they are placing increasing demands on the test floor. An effective test solution must meet final-test requirements presented by the increasing bit densities, the power consumption, and the faster interface speeds of evolving memory devices. The solution will include automated test equipment (ATE) as well as a test handler that conveys devices under test to the ATE, establishes the proper test temperature, and sorts tested devices into bins according to their pass/fail status.

An effective approach to memory test requires a shift away from the memory-test paradigm that has dominated test floors for the past two decades. ATE and test handler companies have regularly increased parallelism, but each doubling in device capacity has been accompanied by a double-digit increase in test-system size. A way forward beyond 512 devices under test (DUTs) in parallel requires thinking beyond the handler or ATE individually to consider the configuration and performance of the entire test cell. Key points to address include the impact of system downtime; the effect of a big, heavy test cell and its footprint; and the test complexity that results from device variation and requirements for testing at multiple temperatures.

A successful memory-test-cell concept will maximize productivity while controlling cost of test through several features:

  • Scalability would enable customers to configure their test cells based on current test requirements while retaining the ability to scale up when necessary.
  • A single test cell would support efficient device evaluation at the R&D stage while offering the flexibility to be repurposed for production.
  • At any level of scalability, the test cell would efficiently utilize floor space and optimize overall operating efficiency.
  • Innovative software would apply artificial intelligence (AI) processing and analysis for tracking handler health and scheduling preventive maintenance. 
  • For installations with more than one test cell, independent asynchronous test-cell operation would allow partial production test to continue even during maintenance on one cell.

Fully integrated test cell’s compact design saves floor space 

Advantest is now offering these features in a new minimal-footprint memory-test-cell family called inteXcell. The inteXcell infrastructure currently integrates T5835 memory tester modules, which incorporate full testing functionality for any memory ICs with operating speeds to 5.4Gbps, including next-generation memories ranging from NAND flash devices to DDR-DRAM and LPDDR-DRAM in BGA, CSP, QFP, and other packages. Throughput can reach 36,500 DUTs per hour.

TC5835 features include an enhanced programmable power supply to assist with testing advanced mobile memories, a real-time DQS vs. DQ (strobe vs. data) function to improve yield, a timing training function that is indispensable for high-speed memory tests, and test time reduction and defect-analysis functions based on various device data patterns. In addition to working with the TC5835, the inteXcell platform is designed to work with future memory-test solutions as well.

The inteXcell tester section consists of three units (Figure 1). The first, the AC rack, operates on 220VAC and delivers power to the test cell. Second, the server rack implements the system-controller, test-processor, and handler-controller functions. Third, as many as four test heads can test up to 1,536 devices in parallel. These three units have been designed to fit together into compact test configurations, eliminating the wasted space that can result when trying to integrate separately developed test-cell units. Consequently, inteXcell occupies one-third the floor space a conventional test cell would require.

Figure 1. The inteXcell tester section comprises an AC rack, a server rack, and up to four test heads.

From engineering to mass production

With inteXcell, ICs can be tested on the same platform from R&D through mass production. Figure 2 shows the scalable parallelism that inteXcell deployments can achieve. At the right, a base inteXcell can test 384 devices in parallel for initial engineering work. That cell can subsequently be repurposed for production. As production volumes increase, inteXcell’s scalable parallelism enables the addition of another test cell, providing a total test capacity of 768 devices in parallel. Moving from right to left in Figure 2, the addition of a third inteXcell brings capacity to 1,152 devices in parallel, while adding a fourth brings total capacity to 1,536 devices in parallel.

Figure 2. The inteXcell’s scalable parallelism provides flexibility for customers.

Reducing downtime

The inteXcell handler unit incorporates a new, compact chamber structure to provide an efficient and highly accurate thermal-test environment over an operating temperature range of -40°C to 125°C or, optionally, from -55 to 150°C.  New functions such as an automatic position correction capability and a one-touch type replacement kit also improve maintainability and reduce downtime.

In addition, new HM360 status-monitoring software comprehensively manages maintenance and temperature data for the handler unit, making it possible to develop predictive maintenance notifications using AI analysis. Sensors might detect, for example, that a handler pick-and-place mechanism is not achieving optimum vacuum levels. By monitoring deterioration in the vacuum performance, an AI algorithm could determine the optimum time to schedule maintenance. As illustrated on the far left of Figure 2, in a four-cell installation, production can continue at 75% capacity when one cell is taken offline for maintenance.

Minimizing need for operator intervention 

The production efficiency of the test process is further improved by the optimization of the test cell’s automated guided vehicle (AGV) or overhead hoist transport (OHT) function, which minimizes operator intervention. As shown in Figure 3a, a traditional flow involves obtaining untested devices from the virgin-device lot stock area and conveying them to a high-temperature test stage. The output of this stage will be either a failed device or one that requires further test. In the latter case, the device is conveyed to the cold test stage. The output will be either a failed device or a good device that has passed both hot and cold tests. As Figure 3a illustrates, this process involves eight operator access points requiring a complex scheduler/dispatcher.




Figure 3. Whereas a traditional test cell requires eight operator accesses for a two-temperature test, inteXcell reduces that number to four and eliminates the need for one lot stock area.

In contrast, inteXcell simplifies the test flow by completing both hot and cold tests with one lot input, as shown in Figure 3b. This approach eliminates the need to establish and access a lot stock area for parts that have passed the hot test, cutting the number of operator access points to four.


Advantest’s inteXcell platform is the first fully integrated and unified test solution to combine broad test coverage with high-throughput handling in a highly flexible system architecture. The new test cells have a compact structure that enables up to 384 simultaneous measurements per cell while using only one-third of the floor space occupied by conventional test systems. inteXcell’s scalable parallelism enables customers to choose the test capacity they need. In addition, each cell employs an independent asynchronous testing capability and AI-based performance tracking, enabling inteXcell to be configured from one to four testers, resulting in high equipment utilization, and streamlined cell-based maintenance. A four-test-cell implementation can test up to 1,536 devices in parallel with high speed and high accuracy. The inteXcell platform is expected to begin shipping to customers in the second quarter of 2023.

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Posted in Featured Products

Advantest Adds System-Level Testing Capability for Advanced Memory ICs

Advantest installed its first enhanced T5851-STM16G tester capable of nonvolatile memory express (NVMe) system-level test coverage at a major manufacturer of IC memory devices. By expanding the capabilities of its established T5851 platform, Advantest addresses the growing market for testing NVMe solid-state drives (SSDs) using ball-grid arrays (BGAs) in automotive applications.

Over the next five years, the automotive market is expected to become the largest consumer of semiconductor devices. This growth is escalating demand for NVMe BGA SSD devices, which are crucial in advanced driver-assistance systems (ADAS). To develop and economically mass produce these key NAND Flash SSD devices, memory manufacturers worldwide need a highly reliable, cost-efficient test solution.

Designed to perform system-level testing of NVMe BGA SSDs, the T5851-STM16G tester is ideally suited for evaluating any generation of BGA SSDs in either an engineering environment or a high-volume production site. The highly versatile platform can handle devices with multiple protocols, including NVMe, UFS and PCIe, at speeds up to 16 Gbps. The system’s modular, tester-per-DUT architecture supports test flows required for system-level testing of up to 768 devices simultaneously. 

Advantest is taking orders for the T5851-STM16G tester. It is available either as a new tester from Advantest’s factory or as a cost-effective enhancement to users’ existing T5851 or even T583X units.

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Posted in Featured

More than Moore or More Moore?

What’s Next in the Future of High-Performance Computing? In this episode, experts will discuss the plans for the coming era of computing and will reveal how the semiconductor industry is continuously evolving to address the looming high performance compute challenges — moving us beyond Moore’s Law. Listen in as John Shalf, Department Head for Computer Science at Lawrence Berkeley National Laboratory, and former deputy director of Hardware Technology for the Department of Energy Exascale Computing Project, helps us uncover how the semiconductor industry will revolutionize HPC over the next decade.

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Posted in Upcoming Events

Advantest’s 2022 VOICE Developer Conference Concludes with Record Attendance

Advantest held its VOICE 2022 Developer Conference on May 17-18 in Scottsdale, Arizona, achieving maximum attendance and sponsorship capacity. Over 300 people attended the event, the majority of whom were Advantest customers and partners. The 2022 conference represented over 60 companies and included presentations of more than 60 technical papers over two days.

VOICE 2022 received 119 abstract submissions from 31 companies across 13 countries. A total of 66 papers were accepted for presentation during the technical breakout sessions, half of which were written or co-authored by customers.

In addition to the technical sessions, VOICE featured a Partners’ Expo, three highly rated keynote speakers, and a first-time “fireside chat” conducted between G. Dan Hutcheson, vice chair of TechInsights, and Manish Bhatia, executive vice president of Global Operations at Micron.

Through the VOICE mobile app, attendees voted to select the best technical presentations and best technology kiosk.  A Visionary Award was also named for ongoing, sustained support of VOICE by a customer.

Best Paper

  • “New ATE Testing Techniques Using PCI-Express with Link Scale-PCIe to Solve Scan, Structural, Protocol and Third-Party Integration Challenges” / Brendan Tully—Amazon, Mike Kozma—Advantest 
  • “Migrating the Test of Medium Power Mainstream SOC Devices Using UHC4T/DPS128 to a Single XPS256 DPS Solution” / Stefan Walther and Linda Hänel—Advantest 

Best Kiosk Award

  • “ACS Edge 2.0” / Sonny Banwari and team—Advantest 

Visionary Award

  • Gabriel Tellechea—AMD 

VOICE is made possible by the organizational work of a Steering Committee, made up of volunteer representatives from Advantest and its customers, and the support of event sponsors, which featured 22 companies, including two new participants this year.

We look forward to hosting VOICE 2023 on May 9-10 in Santa Clara, California. Keep an eye on the VOICE website for more details:

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Posted in Featured Products

Advantest Introduces Industry’s First Flexible DUT Interface 

Advantest launched its DUT Scale Duo interface for the V93000 EXA Scale SoC test systems, enabling the industry’s highest level of parallelism for testing advanced semiconductors. With this revolutionary interface, the usable space on DUT boards and probe cards is increased by 50 percent or more while wafer probe and final-test setups can accommodate component heights that are more than three times taller.

Advantest offers the industry’s first DUT interface with the capability to adapt either to the existing standard DUT board or probe card size or to switch to the new, significantly larger size. Using a unique sliding mechanism, users can effortlessly switch back and forth between both formats to adapt to specific application requirements.

Along with the new interface, a new super-stiff extended bridge achieves superior deflection performance in direct-probing setups. The unit’s universal design gives it the versatility to support a wide range of applications including digital and RF device testing. With its sophisticated sensing capabilities, the extended bridge delivers the industry’s best planarity and high manufacturing yield, ensuring highly accurate positioning and verification of probe card clamping.

“Our new DUT Scale Duo enables the next stepping in parallelism while embodying Advantest’s continuing emphasis on system compatibility by allowing users to utilize their existing DUT boards and probe cards with a new interface,” said Advantest’s General Manager and EVP, Jürgen Serrer. “In addition to protecting customers’ investments, our approach to delivering the most efficient test solutions also offers flexibility and simplifies fleet management on the test floor.”

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