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Advantest’s New TS9001 Time Domain Reflectometry (TDR) System Employs Terahertz Technology to Provide High Resolution Analysis of Circuit Faults

Advantest Corporation announced that it has initiated sales of its new TS9001 TDR System. The new system fully utilizes the company’s unique terahertz technology to enable non-destructive and high-resolution analysis on circuit faults in advanced semiconductor packages, such as flip chip BGAs, wafer level packages, and 2.5D/3D ICs. 

The TS9001 TDR System provides semiconductor manufacturers with flexible solutions for addressing a variety of failure analysis requirements. By establishing a low-cost failure analysis environment and enabling connections to high-frequency probing systems already in use by customers. TS9001 offers customers one of the shortest measurement times on the market. 

Advantest’s leading-edge semiconductor test technology and terahertz failure analysis technology supports the development of innovative semiconductor supply chains, while enhancing the customers’ quality control. 


As semiconductor packages (hereafter, devices) grow smaller and more highly integrated, the ability to locate failures with non-destructive, high-resolution technology is increasing in importance. Providing access to the industry’s most advanced failure analysis environment is critical to being able to address the wide variety of failure analysis issues that are present in these complex devices. To meet these requirements, Advantest developed the TS9001 TDR System, which enables customers to direct-connect their high-frequency probing systems, to obtain high-speed, high-resolution measurement. 

Key Features

  • High-speed and high-resolution measurement

The TS9001 TDR system, which utilizes an ultra-short pulse signal processing technology,  achieves higher distance-to-fault resolution of 5 μm and precise fault location identification with the industry’s fastest class measurement time of 30 sec (Number of integration: 1024, 1/10 shorter than our conventional products). This is the same proven technology used in our ground-breaking terahertz analysis systems.

  • Versatile connectivity for high-frequency probing systems

TS9001 can be configured with a high-frequency probing system owned or selected by the customer. It offers flexible solutions according to the device forms or fault analysis environments. 

(1) Failure analysis of devices with micro bump

By connecting the TS9001 to a high-frequency probing system along with a high-resolution microscope, failure analysis of devices with micro bump of minimum diameter 50 μm is possible. 

(2) Temperature control function

Failure analysis of devices kept in low/high temperatures is also possible, if the system is connected to a high-frequency probing system with a thermal-system function.  

(*) TDR (Time Domain Reflectometry) is widely used to locate circuit failures. Input pulsed signals are reflected at circuit faults inside the device. Time domain analysis of the reflected waveform allows users to determine the fault location and failure mode (open or short) by waveform comparison between good device and failed device. The peaks appearing only in the failed device are analyzed to identify them. 

For more information on this system, visit our Website. 


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New Memory Tester Integrates Burn-In and Core Testing for 5G Product Development

Advantest has added to its H5600 family of memory testers by introducing the new, highly versatile H5620ES engineering test system, designed for both high-speed burn-in and core testing of today’s DDR4, next-generation DDR5, and low-power, double-data-rate (LPDDR) devices in laboratory environments.  By streamlining the number of accessories and reducing the time required between burn-in and core testing, the new H5620ES shrinks the cost of test for evaluating advanced memory devices used throughout 5G applications.  The new system ably addresses all barriers to cost-efficient development and qualification of the newest data-storage ICs that are in high demand for the rapidly growing 5G market.

Like its sister system, the H5620 production unit introduced in March of this year, the new tester delivers high productivity by parallel testing both DDR4 and DDR5 memories. It can accommodate memory ICs with 100-MHz frequencies and 200-Mbps data rates. 

The engineering system is optimized for ease of use in product development, enhancing testing efficiency in the lab prior to production.  Its compact design saves space and enables mobility in laboratory environments while its open-top architecture makes it easy to perform pick-and-place operations without removing the device interface board (DIB).

The H5620ES runs on the same FutureSuite™ operating system as the H5620 production unit, enabling testing with the same waveform.  It also allows pre-testing routines such as contact checking to be conducted on the H5620ES system before transfer to the H5620 tester, thereby reducing cycle times in production.

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Advantest’s New H5620 Tester Performs Both Burn-in and Memory-cell Testing to Address the Rapidly Growing Demand for DDR DRAM Units

Advantest introduced its new versatile, high-throughput H5620 memory tester that combines the capabilities to perform both burn-in and memory-cell testing for advanced DRAMs and LPDDR (low-power, double-data-rate) devices.

With the advent of 5G technology, worldwide DRAM bit-based consumption is expected to approximately double by 2023.  This increase is being driven primarily by growth in the data-processing and mobile-communication market segments, with data centers requiring more memory and smart-phone functionality expanding to include higher resolution, foldable capability and multi-camera designs.  As the average selling prices for memory ICs continue to shrink, semiconductor manufacturers need ways to reduce testing costs while increasing production volumes.

Advantest’s newest tester helps to accomplish this with its superior efficiency.  In production environments, the H5620 can test over 18,000 devices in parallel at 100-MHz frequencies and data rates up to 200 Mbps.  It is adaptable for factory automation and supports a wide temperature range of -10° C to 150° C with a dual-chamber structure featuring individual thermal-control stability.

In addition, the new system can reduce customers’ capital expenditures and save floor space by combining legacy memory-cell testing with the burn-in test process in memory production facilities.

The H5620 runs on the FutureSuite™ operating system with its versatile tool set.  This software ensures that the tester can be easily integrated with legacy memory test systems from Advantest.  In addition, assistance with program coding, debugging, correlation and maintenance is available from Advantest’s global support network.

The new H5620 tester has begun shipping to customers and the H5620ES engineering model will be ready by the second quarter of this calendar year.

H5620 Memory Tester

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Advantest’s New Modules and Test Head Extend the T2000 Platform’s Performance in Evaluating Automotive SoC Devices

Advantest Corporation has expanded the range of its T2000 platform with the launch of two new modules and a test head designed specifically for high-volume testing of devices used in automotive applications.  The new equipment is designed to enhance test coverage, enable higher parallelism and reduce the cost of test for system-on-chip (SoC) devices used in automobiles, a market segment that is projected to have a 9.6 percent compound annual growth rate from 2019 to 2022.

Semiconductor content in automobiles is increasing rapidly as ICs are becoming integral in everything from powertrains and infotainment systems to ADAS (advanced driver-assistance systems) and on-board safety features.   To reach their market potential, automotive SoCs require high-performance, cost-efficient test solutions.

The new RND520 test head has 52 slots, providing the highest pin count available with Advantest’s direct-dock testing option. As a member of the HIFIX (high-fidelity tester access fixture) product line, the new test head supports massively parallel wafer-sort testing.  It covers an area 40 percent larger than its predecessor while using center-clamp technology to ensure stable contact during wafer sorting. In addition, the test head can operate over an extended temperature range up to 175° C.

The enhanced 2GDME digital module leverages 256 channels to test a wide range of SoC devices used in automotive electronics including MCUs, APUs, ASICs and FPGAs operating at speeds up to two gigabits per second (Gbps). It features a dedicated high-performance parametric measurement unit (HPMU) for every 32 I/O channels, giving the unit an expanded current capacity up to 60 milliamperes (mA) for every I/O channel. The module also supports high-voltage applications by enabling electrical stress testing and arbitrary waveform generator (AWG) and digitizer (DGT) functions valuable for characterization purposes.

The new 96-channel DPS192A device power supply facilitates highly parallel testing of automotive SoCs with high pin counts.  This versatile module has a voltage range of -2.0 volts to +9.0 volts and a current range up to 3 amperes. The unit’s capabilities include enhanced slew-rate control as well as a trace function to evaluate power integrity, an averaging function that improves sampling rates for measuring supply currents and a continuous sampling function that enables a new test methodology for IDD spectrum measurement.

The highly flexible T2000 test platform is ideally suited for evaluating SoC devices and other ICs fabricated with small-lot, high-mix manufacturing methods.  The system enables users to respond rapidly to shifting market needs with minimal capital investment while also helping to reduce development times for new designs.





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Evaluating a spring probe card solution for 5G WLCSP

By Krzysztof Dabrowiecki, Feinmetall GmbH, Thomas Gneiting AdMOS Gmb], Jose Moreira Advantest

With the deployment of the wireless 5G standard and its support for mmWave frequencies that allow gigabits-per-second data rates on the consumer market, the semiconductor industry needs reliable and low-cost test solutions. The 5G standard allows mmWave range frequencies from 24GHz to 28GHz—to frequencies as high as 44GHz, and possibly even higher.  To achieve these frequencies requires reliable, highly efficient, cost-effective chip packaging technology. 

From that point of view, wafer-level chip-scale packaging (WLCSP) offers one of the most compact package footprints, providing a high level of functionality, and a frequency range with low resistance and inductance path. Despite having a good thermal performance with a finer pitch interconnection to the printed circuit board (PCB), WLCSP is resilient to extreme variations in stress, drop, and vibration. At the wafer test level, WLCSP technology requires a good and consistent contact resistance, a relatively high contact force with short probes, and above all, an effective online cleaning together with easy onsite repair [1]. With respect to those electromechanical wafer test requirements and with added value such as a frequency performance higher than 28GHz, or a high current capability, the spring pin probe card technology is always a favorite on the test floor on account of its cost and versatility and worthwhile to evaluate for high frequency 5G mmWave applications [2-4].

To define the best possible probe card structure, detailed electromagnetic simulations and analyses are required. RF engineers have several modeling approaches available for this type of simulation, such as a lumped element model (SPICE), distributed element model, or 3D electromagnetic (EM) models. For this study, it was decided to utilize CST Studio Suite 3D EM simulation software.  It allows us to build and analyze an exact and detailed 3D-model of the probe card. A probe card acts as an interconnector on the signal transmission path between the wafer chip and automated test equipment (ATE). Therefore, it is vital to keep in mind that, besides the probe card, there are other challenges with respect to ATE and the PCB side.

On the ATE side, mmWave frequencies already present significant implementation challenges, including the measurement instrumentation and interconnect to the ATE device under test (DUT) test fixture PCB.

Figure 1

Figure 1 shows a picture of the bottom of an ATE mmWave test fixture, where it is possible to observe the blind mating connectors to the ATE system and the coaxial cables. They are connected to coaxial connectors, very close to the socket. The use of coaxial cables in the test fixture is essential because a coaxial cable is significantly less lossy than any PCB signal trace. The PCB test fixture challenges, however, are not the main subject of this paper.

The system assembly and modeling (SAM) framework was used to investigate and optimize a signal path. It consists of multiple individual components, such as wafer bump, probe head, and PCB. These are described by relevant physical quantities such as field magnitudes or s-parameters.  This paper is trying to find an answer and explore three objectives: 1) the impact of different materials and probe head designs on the mmWave performance, 2) analysis of s-parameters and crosstalk, and 3) the probe head design optimization to improve them. Crosstalk is also an important parameter that is taken into account. The presented analysis results reveal the impact of different structure probe head elements on the s-parameter results.

Simulation model

Figure 2

Figure 2 shows an example of what mmWave RF peripheral ports (AN1, AN2) might look like on a 5G DUT. The diagonal bump pitch is 0.4mm, with a bump height of 100mm. The distance, in a row, between RF bumps is 0.566mm. Initially, a spring pin was chosen with uncompressed length L=3.7mm, at working mode L1=3.5mm.  The PCB thickness was 3.8mm and used a hybrid stack-up of the FR4 and Tachyon 100G for dielectric material. The matched trace lengths were designed at 38.8mm. Because of the symmetrical PCB traces layout, the simulation was performed for the critical traces only and one-quarter of the PCB. The RF 3D model analysis includes the wafer solder bump, probe head, and contact with the PCB, in which the traces are included up to the connector locations. 

Figure 3

Figure 3 illustrates a quarter of the probe card model and trace topology.

Figure 4

Figure 4 shows a model of a probe head in contact with the wafer at the bottom and the PCB at the top. The probe head is a 2-layer structure comprising guiding plates and fillers between the plates. The filler layers are the additional materials added between the guiding plates with various dielectric constants and loss tangent. The double plunger spring pins are inserted into drilled holes in the guiding plates and fillers. The pin plunger protrusions at the working mode are formed with a uniform air gap of 0.1mm between the head and the PCB, and 0.25mm between the head and wafer. The created 3D simulation model allows quick verification of results to identify appropriate material properties and geometry before building a test probe card.

Initial simulation results

It is well-known that any impedance mismatch in the signal path will have an impact on the return loss and in that way, degrade the measurement path performance. Therefore, impedance is a crucial parameter to be checked and controlled. In the PCB industry, the common impedance specification is in the range of 50 +/-10% Ohm for a single ended signal. But 5% is possible in certain cases, though at a very high cost.

Figure 5

Figure 5 shows the simulated time domain reflectometry (TDR) plot for the model with various filler materials wit a time rise of 29.2ps (for 30GHz). The dashed lines indicate the maximum and minimum impedance tolerances. In the figure, it can be noticed that the air gap between the guiding plates causes an impedance discontinuity that peaks at

70 Ohms. The material option 1 shows a drop in the impedance discontinuity peak at 41 Ohm. The material B options 2 and 3 significantly reduce the impedance discontinuity to an acceptable range. As a consequence of material B air and option 1, the insertion loss and return loss had a limited frequency bandwidth, as shown in Figure 6. In this case, the dashed lines reveal acceptable limits of -1dB for insertion loss, and -10dB for return loss.

To read full article please visit Chip Scale Review December 2019 issue, page 14:


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New End-to-End Test Solutions for 5G, Automotive and IoT

Advantest’s new MPT3000ARC is the industry’s first test platform to combine thermal-control capability with high throughput, enabling extreme thermal testing of solid-state drives (SSDs).   Adding this new system to the MPT3000 product family, which is already in wide use by SSD manufacturers, Advantest is supporting SSD testing from design to manufacturing, providing the fastest, lowest risk path to market for next-generation devices, including PCIe Gen 4. In addition to meeting automotive thermal test standards, the new tester’s automation-ready thermal chamber enables SSD manufacturers to quickly ramp temperatures, which optimizes Reliability Demonstration Test (RDT) and results in faster time to market.  With the addition of the MPT3000ARC, the MPT3000 series enables rapid changeover to provide a single-system test solution for a wide variety of SSD products, from 40-mm M.2 memories to larger EDSFF devices.

The MPT3000ARC’s unmatched resourcefulness is a key advantage in the continually shifting and developing SSD market, designed to enable mission-critical testing across a broad range of SSD form factors and protocols. The single-system solution allows SSD manufacturers to easily evolve from testing PCIe Gen 3 devices to Gen 4 devices by simply changing a board and downloading firmware. This new tester provides the fastest path to bring PCIe Gen 4 SSDs to market while also minimizing risks, reducing test development time and accelerating new product validation, debugging and production tests.

The continuing growth projected for the solid-state drive (SSD) market requires device manufacturers to find a highly flexible test solution capable of supporting their expanding product portfolios at a low cost of test. Advantest’s new MPT3000ARC s tester is designed with the full spectrum of capabilities to handle all SSDs, including not only the most advanced PCIe Gen 4 memories, but also the highest performing enterprise drives and the most cost-effective client devices used throughout mass-market connected devices, from smart cars to wearable electronics.

With an increasing number of SSDs being used in rugged thermal environments, these memory devices must be proven to withstand harsh conditions. The MPT3000ARC features an innovative thermal chamber that allows it to operate over a broad range of temperatures, satisfying automotive and industrial thermal-testing standards. This makes the tester ideally suited for reliability demonstration testing (RDT) for the rapidly multiplying array of applications.

The MPT3000ARC applies the same proven architecture, software and performance already in wide use by SSD manufacturers worldwide. Its production-compatible ergonomics and automation-friendly chamber access make it suitable for high-volume SSD testing.

By using changeable and customizable interface boards, this tester has the versatility to handle virtually all SSD form factors, from 40-mm M.2 memories to larger EDSFF devices. The system’s design enables quick and easy switching of interface boards, enabling rapid changeover to support a wide variety of SSD products on a single system.

As the newest member of Advantest’s MPT3000 product family, the MPT3000ARC is fully integrated. Its efficiency and performance are optimized by leveraging the same tester-per-DUT architecture, site modules, power supplies and hardware acceleration as all other systems in the MPT3000 series.

View video to learn more.

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