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Trends in Testing: New Challenges Create New Opportunities

By Doug Lefever, Senior Executive Officer, Advantest Corporation, and President and CEO, Advantest America

As advancements in semiconductors and microelectronics soldier ahead into emerging, even uncharted, territory, new test challenges arise. To that end, let’s look at a few key trends and challenges that are driving opportunities for innovation in the test sector.

Technology convergence has been a buzzword for some time, and this trend is only going to intensify with the heightened need to move, access, and analyze massive volumes of data. As a result, data analytics technologies (Big Data, artificial intelligence [AI], and machine learning) will continue to play a vital role in driving test efficiencies – not just operational, e.g., improving overall equipment efficiency (OEE), but also transformational: enabling data to feed forward and backward between test insertions, as well as outside of test. The reality is that the lines are blurring between the front and back ends of test, and the insertion points change, depending on device type and lifecycle status. So, the test flows that happen throughout the lifecycle of the device need to be flexible.

Complex high-performance computing (HPC) and AI devices are growing very large, and because of interposers and bridging, their power requirements can exceed 1000W. This means that we need to be able to manage temperature with a high degree of precision during testing. These large devices also require additional compute and analytics capability during test. To this end, we developed our ACS Edge solution, which essentially adds a supercomputer alongside the tester to open up compute power and start to enable real-time adaptive test.

With these developments, the system will become enormously complex, requiring verification of entire systems (hardware, firmware/embedded applications, and software). This means we’ll be seeing a broader deployment of system-level testing (SLT) for both systems and modules, as well as SLT/ATE at the probe level for known good die, including active thermal management solutions. To this end, we’ve incorporated into our offerings the test-related accessories we acquired upon purchasing Essai, including sockets, thermal control units and other test subassemblies. Our value proposition rests in our ability to address the full hardware stack and in the comprehensive nature of our offerings.  

In the broader test arena, generation, validation, and optimization of required test content such as scan vectors, built-in self-test (BIST), and functional test (software code) will need massive support and cooperation between the EDA and ATE industries. Advantest has established strong relationships with the leading EDA providers to help drive these efforts. The industry is also going back and mixing functional tests more with structural tests, and more design-for-test (DFT) techniques are being added. While increased scan, serial high-speed scan over USB, and PCIe ports are being used, that still isn’t enough, which brings us back to SLT continuing to be deployed.

For 5G, test solutions are largely in place. Some high-volume manufacturing (HVM) device interfacing/interconnect technologies like over-the-air (OTA) are coming along, while test development is starting for advanced millimeter-wave (i.e., THz, 6G). There will also more use of on-chip sensors and agents to monitor device performance all the way through the fab, assembly and in-field. This traceability is vital to ensuring ATE plays a critical role in pulling data from sensors – this heightened need for data extraction and analysis is a recurring theme that permeates everything going forward.

Continued electrification of cars will also drive lots of growth in test, including challenging areas like high voltages – i.e., those greater than 1kV – which require different kinds of methodologies. These higher voltage requirements are also needed for silicon carbide (SiC) applications in vehicles. SiC, like gallium nitride (GaN), has been around for a long time and is finding new life in applications such as battery management. We can cover this with our mixed-signal configurations and our integrated power solutions.

With respect to packaging, we expect to see a bifurcation in the industry: HPC/AI will move to 2.5/3D ICs, while mobile will remain on monolithic 2D for a little while longer. We’re already into 2.5 and 3D, and we have been for some time. However, with hybrid bonding and die stacking, we’re moving into 3D IC. When that is fully implemented, it will bring some tough new challenges. We believe a holistic approach is required to create high-power solutions that will then be coupled with other chips in a package.

In addition, there will be new approaches to address the “memory wall,” such as large eRAMs, 3D stacked RAMs, co-packaging on 2.5D or access via serial I/O. Power consumption of I/Os may also drive the integration of optical I/O. The first step will be co-packaged optics (CPO), which involves heterogeneous integration of optics and silicon on a single packaged substrate aimed at addressing next-generation bandwidth and power challenges. 

As you can see, many technology trends have test requirements that overlap or coincide, with demands created by massive amounts of data generation and processing playing a massive role. Testing at the exascale level requires powerful equipment that can handle the challenge. We are meeting this challenge with our EXA Scale test system, built on our flagship V93000 architecture, which addresses the challenges of very high scan-data volumes, extreme power requirements, fast yield-learning and high-multisite configurations.


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Automotive Keyless Entry SoC Test Methodologies and Techniques

By Philip Brock, Applications Engineer & Consulting Manager, Louis Benton, Jr., Applications Engineer & Consulting Director, Advantest, and Jonvyn Wongso, Technical Staff Test Engineer, Microchip

Note: This article excerpts content from the Virtual VOICE 2021 Best Paper, voted on by conference attendees. Jonvyn Wongso, Daniel Marstein & Krishna Vangapalli from Microchip Technology co-authored the original paper, and their research and development efforts were invaluable to this project.

Passive Entry Passive Start (PEPS) technology has become standard in the automotive market for keyless operation. A secure wireless communication system, PEPS enables to lock and unlock the vehicle, start and stop the vehicle without physically using the key. Electronic functionality embedded in the key fob to interact with the vehicle (see Figure 1) includes passive start and stop, passive lock, remote keyless entry, immobilizer, key fob wake-up, and key fob localization. These functionalities are controlled by the primary modules embedded within the fob itself. The immobilizer provides access to start the vehicle when the key fob’s battery level is low by placing the fob at the start button and pressing it.

Figure 1: This diagram illustrates how components within the key fob correspond to functionality in the car itself.

The PEPS-to-vehicle ecosystem requires several key modules to function that includes a low-frequency (LF) transmitter, an immobilizer, a Radio Frequency (RF) transmitter (key fob) and transceiver (vehicle side), as well as a microcontroller (MCU). Each module in the key fob poses specific testing challenges and restrictions, necessitating a test plan and flow optimized for the testing of the key fob’s circuit, as shown in Figure 2. 

Figure 2: The key fob architecture depicts the main components within the key fob and a representation of how each component is tested on the Advantest V93000 test system.

The coverage percentages at the upper right in Figure 2 represent the overall test flow’s test time. Approximately two-thirds of the test coverage is dedicated to the LF structure (analog) and the MCU (digital), with another 19 percent focused on power management and parametric tests. The remaining 6 percent of the test coverage involves testing of the RF module with transmission functionality at sub 1 GHz band with no RF reception capability.

The combination of test requirements to accommodate all the different technologies housed within the PEPS key fob makes it an ideal device for demonstrating the versatility of the Advantest V93000 SoC test platform, including the AVI64 and PS1600 pin cards. A test solution is designed with comprehensive methodologies to test every module in the key fob. The balance of this article summarizes the key aspects of the test approach.

PEPS test methodology elements


Digital testing utilizes two standard methods to communicate to the IC:

  • Serial programming interface (SPI) – Standard communication protocol is used to test all non-MCU (non-digital) structures via direct access to the RAM. However, due to the slow communication speed compared to HVSP protocol, the programming time to the EEPROM is approximately 10ms per byte.
  • High-voltage serial programming (HVSP) – Used for FLASH and MCU core test with fast access to the EEPROM, this proprietary protocol is much faster than SPI, with a FLASH and EEPROM programming time of 3 to 4ms per page (each page is 16 bytes long).

One key digital test that has to be performed is to measure the time to program a page to the FLASH (16 bytes). The page program completion time varies between devices. The typical test method to measure and detect the end of the programming time is by implementing a match loop counter opcode in the pattern vector as the device asserts a state of a pin to high when the programming event has completed. However, the implementation of this method prohibits the use of the PS1600’s Time Measurement Unit (TMU) function on the same channel pin in parallel to measure the page program time accurately.

The test methodology developed involved the use of the Rapid Development Interface (RDI) API, a code structure that wraps Advantest’s standard application programming interfaces (APIs). The API is based on object-oriented programming that encapsulates firmware commands, enabling seamless execution of multiple commands. This creates a competitive advantage by dramatically streamlining the software development, and with the V93000’s multiport capability, it enables higher timing resolution that can be achieved on a specific pin or pin group. The use of the comparator functionality allows to strobe for a level change in the signal for a fixed amount of time.

Power Management

The Brownout detection circuit in the PEPS is a challenge to test to achieve optimized test time. In a typical test method, a voltage sweep is conducted from high to low to detect the brownout state threshold, followed by a voltage sweep from low to high to search for the recovery threshold level. An experiment was conducted with the implementation of four different test methodologies to determine the most optimized method to test the Brownout Detection circuit, summarized in Figure 3. In summary, the implementation of the Per Pin Parametric Measurement Unit (PPMU) as the Arbitrary Waveform Generator (AWG) yielded the fastest test time with minimal test instrument latency dependencies.

Figure 3: Investigation of four different brownout detection methodologies – PPMU as AWG methodology consumes a fraction of the test time in comparison with the other three options

Low Frequency Test

The Receiver Signal Strength Indicator (RSSI) circuit in the key fob indicates the proximity and location of the key fob with respect to the vehicle. The 3D LF pins are transponders with signal transmission and detection  at a frequency of 125 kHz with detection amplitude levels as low as 1.0 mV peak differential. The LF test requires a complex on-board circuitry in order to source AWG amplitude levels from 1 mV up to 8 V peak. Due to the real estate demand from the load board to implement these circuits with amplitude ranges, the extra-large size load board is used, extending out on both sides of the tester’s field. The RSSI value may only be read out after the completion of conversion of the LF signal level from a specific register in the device. In addition, there is a register that may be continuously read to check for status of the RSSI conversion.

Therefore, the proper test methodology for this test is to implement the Condition Go-No-Go (COGO) API from RDI to continuously check for the status of the conversion. This method corresponds to the device’s application. However, due to the inherent long latency to judge each event using COGO (described in Figure 3), a one-time fixed time delay was implemented prior to the readout of the RSSI conversion.

The other primary LF test involved the transponder, which is used for the immobilizer. The key fob that is placed at the start button of the vehicle will be energized by the vehicle’s coil that is located around the start button to enable communication between the key fob and the vehicle. This test requires both the AWG and Digitizer (DGT) instruments to source and capture the modulated waveform on the LF pins.

The communication between the key fob and the vehicle compromises of three stages as shown in Figure 4 – startup (energizes key fob), write mode (vehicle transmit authenticated message to key fob) and read mode (key fob responses with another authenticated message). The post processing of both the sourced and received waveform uses custom Digital Signal Processing (DSP) functions along with built-in V93000’s DSP APIs. 

Figure 4: Transponder communication between key fob and vehicle on LF pins on key fob.

RF Test

The Amplitude Shift Keying (ASK) modulation is used to transmit RF authenticated signal from the key fob to the vehicle. It is critical to test the duty cycle of the modulated signal that has a period of 12.5 us, toggled by an external pin when set in test mode. The device itself operates at a 2 us period. Therefore, multiport has to be implemented for the sequencer to drive two groups of ports at different periods. This test methodology also includes RF site interlacing technique, taking advantage of the V93000’s eight-site parallel test capability with 2 RF FE24 cards. Figure 5 illustrates the test criteria and methodology employed. Post-processing involves the capture of complex waveform, conversion of the waveform to rms in order to create the burst envelopes, performing moving average to filter out noise and searching for all falling and rising edges to calculate the duty cycle. 

Figure 5: The transmit ASK duty cycle test methodology is summarized here.

Software/hardware techniques

The LF testing requires sharing of the AWG and Digitizer instruments (MCE 4 source and 4 measure units) across 8 sites, thus increasing test time and reduces multisite efficiency. The implementation of SEMI_PARALLEL block in the test method enables execution of a single test cycle, hence maximizing multisite efficiency. Sequencers connected to AWG and DGT are placed in the SEMI_PARALLEL block as shown in Figure 6. Method 1 is the most common implementation. However, the setup pattern will be executed more than once on the same site. In contrary, method 2 is the least efficient but may be an option if the setup pattern may only be executed once to each site to avoid change of the state of the device.     

Figure 6: Shown here are the two most common SEMI_PARALLEL block test flow methods for shared resources.

Another test method technique implemented as part of the test solution includes the use of both RDI and MAPI APIs to resolve per site device failure on a specific mode or event as shown in Figure 8. RDI is used for the initial generation and execution of the pattern. MAPI APIs are subsequently used to re-execute the RDI generated pattern to specific failed sites. This method allows the recovery of the device(s) within the test method to save test time and not applying stimulus and retesting already passed sites.

Figure 7: The combination of RDI and MAPI usage enables device per site failures to be resolved.

On the hardware side, the use of relay driver circuit (SN74LS04DR followed by MDC3105LT1G) enables the drive of eight relays simultaneously such as G3VM-41QR10TR05 only by using a single utility pin. This technique enables the implementation of many circuit paths on the load board but omits the need of a PMUX card in the tester. Subsequently, the test load board design requires calibration of every signal path and circuit for each test site. There is an on-board EEPROM that stores the calibration offset and losses. Due to the limitation of memory space in the EEPROM, every calibration value is compressed using IEEE754 floating point standard. Depending on the accuracy requirement, this method enables greater than 50-percent compression rating of a decimal value. 

In summary, there are many challenges in both hardware and software development to create a test solution for optimized test time and efficiency, as summarized in Figure 8.

Figure 8: Summary and challenges of PEPS key fob test solution.

Since this device is targeted for automotive application, it has to be tested at cold, room and hot temperature ranges. Temperature variations affects the performance of the circuitry on the load board and has to be calibrated for each temperature range. The MCU core has to be tested at multiple different voltage level that requires synchronization of the pattern sequencer for each level change. In addition, testing the LF circuit requires extensive changes in the AWG’s amplitude level that requires additional setup and execution time that may increase test time and lower efficiency.

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HSIO Loopback Turns Challenges into Opportunities for Test at 112 Gbps

By Dave Armstrong, Principal Test Strategist, Advantest, and Don Thompson, Senior Director of Engineering, R&D Altanova

For both PCIe and Ethernet (IEEE 802.3) signals are getting mighty small. With PCIe 5 reaching 32 Gbps (NRZ at 32 GBaud) and 802.3 reaching 112 Gbps (PAM4 at 56 GBaud), typical eye-mask limits are shrinking. Consequently, test requirements for high-speed I/O (HSIO) test are becoming daunting.

HSIO test involves measurement of Tx eye height and width, confirmation that a receiver can detect a low-level signal, and confirmation that continuous time linear equalization (CTLE) is effectively compensating for insertion loss. In addition, the test must verify bit error rate and confirm that a receiver can receive an off-frequency or out-of-phase signal. Yet another requirement is DC access for continuity and scan test.

Traditionally, HSIO loopback has been the preferred approach to HSIO test, with a simple wire or capacitor connecting a DUT’s Tx to Rx inputs. Loopback itself comes in various forms. The simplest form is internal loopback in which the device talks to itself and never exercises the transceiver circuitry; it can test internal logic only.

Another method is AC-coupled external loopback which does exercise the I/O circuitry, but like internal loopback, it does not perform Tx/Rx eye tests, and it does not test pre-emphasis and equalization. AC-coupled loopback is easy to lay out on a DUT board, but the signal level the Rx receives is too low loss / too hot, making the test too easy. Similarly, when connecting channel pairs for loopback tests, the Tx/Rx pairs share the same PLL/DLL, again making the test too easy. 

There are some workarounds that can be used on an AC-coupled external loopback. Long circuit-board trace lengths could help make AC-coupled test more realistic, while connecting the Tx of one signal pair bank to the Rx of another would mitigate the problems of a shared PLL/DLL. And the addition of bias tees loopback circuits would support DC and continuity (Figure 1).

Figure 1. AC-coupled external loopback test with bias tees for DC test.

However, these loopback tests do not provide sufficient visibility into the DUT that would aid in diagnosis, making them ineffective, particularly at speeds as high as 112 Gbps.

With the addition of some high-performance MultiLane instruments, one can improve on the simple loopback tests significantly. The Advantest V93000 platform supports two very different approaches for HSIO test: 16-Gbps test with the Advantest’s Pin Scale Serial Link (PSSL) card or 112-Gbps test with the MultiLane test-head resident instrumentation. 

The MultiLane approach supports a 112-Gbps PAM4 bit-error-rate tester (BERT). Based on a benchtop BERT, the AT4039E is configured as an eight-lane cassette that fits under a V93000’s DUT board, keeping signal paths short. In a similar fashion, the AT4025-50, which is the heart of the approach suggested in this paper, is a 50-GHz digital sampling oscilloscope (DSO), configured with eight channels per cassette, with 32 channels maximum per system. This complements the BERT and also fits underneath the V93000’s DUT board. The different types of instrumentation have their own advantages and disadvantages, each leaving some gaps in measurement coverage (Table 1).

Table 1. Instrument-based test capabilities for NRZ and PAM4 signaling.

A combination of instruments and a technique we call “BIST plus scope-sampled loopback” can fill the gaps while keeping instrumentation costs low and test times short. BIST plus scope-sampled loopback adds a splitter that provides a signal path to the DSO (Figure 2). 

In contrast to the PSSL or a BERT where test patterns originate and are received, the scope-sampled loopback technique makes use of the DUT’s BIST circuitry to generate a pseudo-random bit stream. The DSO can monitor this data stream while it is looped back to the DUT receiver in order to provide a comprehensive report on device performance during this real-world usage. Not only does this provide the user with valuable parametric data on the SerDes performance, it allows one to clearly differentiate between Tx and Rx problems. This approach also provides 6 dB of attenuation, more closely mimicking actual operation than does the standard AC-coupled loopback test, thereby overcoming the drawback of a test being too easy. Adding a programmable attenuator can provide an even more thorough test.

Figure 2. AC-coupled loopback test with a splitter providing access to a digital sampling oscilloscope.

The sampled-loopback technique does require some DUT-board real estate. One example of an AC-coupled loopback circuit with a splitter paired with an attenuator requires about 234 mm2 vs. 48 mm2 for an AC-coupled implementation with bias tees. The valuable data a DSO can capture using the technique can justify the additional DUT-board real-estate cost.

Sampled loopback also poses DUT-board layout challenges regarding trace losses and via impedances at 112-Gbps frequencies.  Tester signals connect on the bottom of the DUT board and make their way to a socket on the top.  This requires multiple vias and several inches of matched PCB traces to ensure that each lane sees the exact same interconnect length and attenuation (Figure 3).

Figure 3. DUT board showing insertion loss and impedance discontinuities.

The margin of error is small, requiring high-speed dielectrics (lossy dielectrics are sometimes used to stress the link) with trace widths typically between five and seven mils and prioritizing loopback circuit placement to keep trace lengths kept short. 

DUT boards are typically between 0.200 in. and 0.300 in., which pose signal-integrity challenges for vias.  Tuned-impedance vias are required to reduce insertion loss and must be a key focus for successful DUT-board designs at 112 Gbps. Finally, socket performance is also critical, and the socket cannot be an afterthought.

High-speed design requirements mandate effective SI simulation and optimization with all circuits modeled and included in the simulation well before the design is completed. 

Once fabricated, careful VNA measurements should be performed to confirm that design goals were met. Fortunately, a tightly integrated design-to-fab process can meet the requirements of DUT-board layout to support the BIST plus sampled loopback technique. High-frequency design validation closes the control loop on the design-to-fab process, providing proof of simulation accuracy, proof of board fabrication execution, and proof of final board performance. 

Initially, adding sampled loopback on all lanes supports the use of many DSO channels during characterization to speed data gathering. In production, you can make use of the characterization data to determine which lanes should continue to be monitored. Ultimately, for a mature product, the hope is that the DSO is no longer needed to monitor any channels.

Sampled loopback offers several advantages. For example, production software can support sampled loopback with the addition of scope code to check the DUT output.  In addition, the scope serves as a calibrated observer, a function not available with a device communicating with itself in a standard loopback test. PLL/DLL/VCO issues are some of the most common issues with SerDes interfaces and are best detected with the scope approach.  Finally, scope measurements are much faster than BERT measurements. 

Table 2 shows the scope sampled loopback technique closes the gaps in Table 1.

Table 2. Test and measurement gaps closed through the use of the BIST plus scope-sampled loopback technique.


In summary, early data and experience suggest that simple internal loopback, which tests only the ability of a part to talk to itself, is inadequate for testing many high speeds ICs. The addition of a calibrated external instrument such as the MultiLane DSO via sampled loopback provides the ability to identify problems that would otherwise be missed at 112 Gbps. 

Advantest can apply its years of experience in high-speed digital test to help you implement a BIST plus sampled-loopback strategy, and R&D Altanova can assist with the design of the very complex DUT boards supporting 112-Gbps data rates for the V93000 tester.


This article is based on the award-winning VOICE 2021 presentation “HSIO Loopback—The Challenges and Obstacles of Testing at 112 Gbps,” by Dave Armstrong, Advantest, and Don Thompson, R&D Altanova. 

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Study Confirms 1.82-mm Coaxial-Interconnect Design Target for mmWave ATE

This article is a condensed version of an article published March 12, 2021, in Microwave Journal. Adapted with permission. Read the original article at

By Jose Moreira, Senior Staff Engineer, SOC R&D, Advantest

The adoption of mmWave frequencies for applications such as 5G and WiGig creates new challenges for the ATE industry, including the need for a reliable blind-mate interconnection between the printed-circuit-board (PCB) test fixture and ATE measurement instrumentation. An ATE system requires multiple types of interconnects (Figure 1). Spring-pin interconnects predominate for power and digital. RF and mmWave signals require coaxial interconnects, due mainly to the isolation requirements, not just the frequency range. The ATE must also automatically mate to the PCB test fixture without any kind of manual interaction. 

Figure 1: This depiction of Advantest’s V93000 ATE system top-side shows the different interconnects for digital, power, RF, and mmWave.

A key requirement is interconnect reliability; for mmWave ATE applications, the interconnect must support 20,000 insertions while guaranteeing ATE system specifications. A reliability study demonstrates that a blind-mate 1.85-mm coaxial interconnect achieves this design target with a significant margin.

Figure 2 shows the bottom side of a mmWave ATE test fixture and the different mating interconnects. For the spring-pin-based interconnect, a plated via connects to the spring pin tip and to a PCB signal trace, which is then routed to the DUT. A coaxial mating connector handles RF and mmWave signals. A coaxial cable from the coaxial interconnect in the test fixture connects to another connector close to the DUT socket. Unlike a PCB signal trace, the coaxial cable provides layout flexibility and, more importantly, significantly lower loss, since even a thin coaxial cable is less lossy than the best PCB signal trace.1 

Figure 2: This view of the bottom-side of an Advantest V93000 ATE test fixture shows the mating connectors and signal routing.

1.85-mm interconnect design

Reference [2] describes the development of a 1.85-mm blind-mating interconnect design (Figure 3), which provides mode-free operation to 70 GHz with no interconnect failure for 20,000 docking cycles. The IEEE 287 standard-compliant3 1.85-mm female interface on the nonmating side of the interconnect uses off-the-shelf 1.85-mm cable assemblies to connect the blind-mating interface to the ATE measurement instrumentation and to the connector in the PCB test fixture close to the DUT. 

Figure 3: The blind-mating spring-loaded 1.85-mm interconnect requires mode-free operation to 70 GHz with a guaranteed 20,000 docking cycles.

Figure 4 shows the 1.85-mm blind mating connector pairs implemented on the ATE system and DUT test fixture sides. The system supports a maximum of 64 mmWave interconnects. The connector interface is spring-loaded on the male, ATE interface side and designed to self-align as the interface is mated. The mating action is part of the test fixture docking process to the ATE system. The ATE interconnect interface (Figure 2) comprises several interconnects apart from the 1.85-mm blind-mate connectors, all of which require a large docking force and, in turn, require special care with the mechanical design of the entire docking interface. This blind-mating interconnect requires a constant specific pressure on the entire mating surface to achieve the required 70-GHz frequency bandwidth. If this pressure is not correct or homogenous, effects like in-band resonances will appear in the interconnect frequency response.

Figure 4. This illustration depicts 1.85-mm blind mating connector pairs implemented on the ATE system and DUT test-fixture sides.

Reliability measurement procedure

Unfortunately, no clear guidelines have been published for evaluating the reliability of a blind-mate interconnection. Using the IEEE 287 standard3 as a guide and considering available resources, we developed a reliability test plan using a set of 14 connectors. Ten connectors were used for a docking cycle test to the maximum number of 60,000 insertion cycles. We measured S-parameters after every 300 cycles and removed the connectors to perform optical and mechanical measurements after every 6,000 cycles. Due to measurement resource limitations, we tested only two interconnects in parallel.

To eliminate the possibility that individuals in a pair become adapted to each other across the test run, after every 6,000 cycles, we exchanged the female of the pair between the two connectors being tested in parallel. Otherwise, measured reliability results could be significantly better than what you would find in a real application, where different test fixtures connect to different ATE systems through the lifetime of the connector.

Two other connectors were stressed to 60,000 cycles; in this case, only contact resistance measurements were performed every 300 cycles. Similarly, the same physical measurements and female connector exchange were performed every 6,000 cycles, as previously described.

Finally, the remaining two connectors in the measurement set were subjected to an accelerated life test, where they were left in a climatic chamber for 72 hours at 85°C and 85% humidity followed by the 60,000-docking-cycle test, with S-parameters measured every 300 cycles.

Measurement results

Our reliability testing strategy generated an enormous amount of data, which is summarized below and discussed in detail in Reference [4]. 

The S-parameter measurement setup consisted of an Anritsu MS4647B VNA and a 4-port extension MN4697B as well as Megaphase RF Orange 1.85-mm measurement cables. The VNA was used without calibration, so the loss shown includes both the coaxial cables’ and the VNA’s intrinsic loss. We employed this approach because our objective is to measure variations of interconnect performance over an increasing number of docking cycles, not the intrinsic connector performance. 

Figure 5 shows the interior of one connector pair before the test, at 30,000 cycles, and at 60,000 cycles, showing degradation of the socket side in the female of the pair. 

Figure 5: These successive images depict the interior of the connector pairs at different numbers of cycles.

Figure 6 shows the measured S-parameters after 60,000 insertion cycles. Since S-parameter measurements were performed every 300 cycles, the graph contains 200 overlaid plots. After cycle 54,000, a resonance appeared in the measured insertion loss around 20 GHz, revealing a failure of the interconnect, even though it continued working at higher mmWave frequencies. The cause for the failures was a crack in one of the socket fingers. This is the same mechanism seen with all failed connector pairs—not surprising since finite-element mechanical simulation shows this point has the highest mechanical stress during connector mating.4

Figure 6. After cycle 54,000, a resonance appears in the measured insertion loss at around 20 GHz.

Figure 7 shows the measured |S11| and |S21| parameters for a connector with no resonance failures during the entire 60,000-cycle test. This measurement was done with a fully calibrated VNA before the start of the test and after the entire 60,000 cycles. The results show even after 60,000 cycles, measured insertion and return loss are still acceptable.

Figure 7. This diagram shows the measured |S11| and |S21| for a connector with no resonance failures during the entire 60,000-cycle test.

Additional considerations

Although from a test and measurement perspective, electrical performance is the critical metric, the IEEE 287 standard defines several mechanical metrics, including the connector socket’s withdrawal and insertion forces.3 Another important metric is concentricity, the difference between the center of the inner and outer diameters of the socket and pin. In addition, computed tomography (CT) provides additional information regarding connector reliability. Figure 8 compares the surface of the original connector at cycle 0 to the connector’s surface at cycles 12,000 to 60,000 by visualizing the deviation in microns of the connector surface compared to cycle 0. Resolution is in the range of single-digit microns. 

Figure 8: CT scans performed on one of the interconnect female connectors at different stages of the cycle testing show successive deviations.

And finally, it is worth noting that the 1.85-mm connector standard offers many advantages for the blind-mate interface. For example, the long length of mechanical engagement of the adapter housing protects the center conductor while acting as an electromagnetic interference shield. A recent Microwave Journal article,5 on which this article is based, provides more information on the connector, mechanical metrics, concentricity, and CT scanning as well as additional details on our connector reliability test plan and on the mechanical finite-element simulations we used to confirm the specific failure mechanism we detected.


Our reliability study of a blind mate 1.85 mm coaxial interconnect for ATE mmWave applications shows that the target of 20,000 insertions was achieved with a significant margin, since all the connectors in the study failed above 40,000 cycles, excluding the connectors that had the accelerated life procedure performed. 


We thank Kosuke Miyao, Andy Richter, Marc Moessinger, and Matthias Feyerabend from Advantest; the Advantest failure-analysis lab in Gunma, Japan; and Eric Gebhard from Signal Microwave. We also thank Professor Sven Simon and Peter Gaenz from the Department of Parallel Systems at the Stuttgart University for the CT scan measurements.


  1. J. Moreira and H. Werkmann, Automated Testing of High-Speed Interfaces, Artech House, Second Edition, 2016.
  2. B. Rosas, J. Moreira, and D. Lam, “Development of a 1.85 mm Coaxial Blind Mating Interconnect for ATE Applications,” IEEE International Microwave Symposium, 2017.
  3. “IEEE Standard for Precision Coaxial Connectors (DC to 110 GHz),” IEEE 287-2007, September 2007.
  4. A. J. Rodrigues Mendes, Reliability Evaluation of a 1.85 mm Blind Mating Coaxial Interconnect for mmWave ATE Applications, Master of Science Thesis, Instituto Superior Técnico, University of Lisbon, 2020.
  5. Moreira, Jose, et al., “Development and Verification of a 1.85 mm Coaxial Interconnect for mmWave ATE,” Microwave Journal, March 12, 2021.


Figure 1: This depiction of Advantest’s V93000 ATE system top-side shows the different interconnects for digital, power, RF, and mmWave.

Figure 2: This view of the bottom-side of an Advantest V93000 ATE test fixture shows the mating connectors and signal routing.

Figure 3: The blind-mating spring-loaded 1.85-mm interconnect requires mode-free operation to 70 GHz with a guaranteed 20,000 docking cycles.

Figure 4. This illustration depicts 1.85-mm blind mating connector pairs implemented on the ATE system and DUT test-fixture sides.

Figure 5: These successive images depict the interior of the connector pairs at different numbers of cycles.

Figure 6. After cycle 54,000, a resonance appears in the measured insertion loss at around 20 GHz.

Figure 7. This diagram shows the measured |S11| and |S21| for a connector with no resonance failures during the entire 60,000-cycle test.

Figure 8: CT scans performed on one of the interconnect female connectors at different stages of the cycle testing show successive deviations.

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SLT Enables Test Content to Shift Right to Optimize Test Efficiency and Part Quality

By Dave Armstrong and Davette Berry, Directors of Business Development, and Craig Snyder, Business Development Manager

Increasing device complexity and the continuing drive for higher levels of quality are fostering a reconsideration of test strategies. To be effective, test engineers must choose how to optimally deploy test content, from wafer probing to system-level test (SLT). A March 2019 TestConX presentation1 outlines how test content is typically allocated—for example, final test performs structural and functional tests, parametric measurements, and performance binning; burn-in screens for early-life failures; and SLT looks for mission-mode failures resulting from hardware and software interactions. For cost balancing, though, it might be preferable to transfer a test step that has traditionally been performed at final package test, for example, upstream toward wafer test or downstream to SLT. At Advantest, we call the upstream transfer “shift left” and the downstream transfer “shift right” (Figure 1).

Figure 1. The test flow from wafer probing to SLT offers opportunities to shift test content right or left to optimize test efficiency and part quality.

Shift left overview

A January-February article2 in Chip Scale Review describes the shift left process, which is particularly applicable to the integration of heterogeneous known-good die (KGD). For KGD test, it is advantageous to shift test content left from final test toward wafer test or to a singulated-die test stage, where you can perform full-power active-thermal-control (ATC) testing at speed. For KGD, a shift left strategy of more testing sooner reduces the number of good die scrapped because of one bad part in a multi-die assembly, ultimately leading to lower costs and more profit.

SLT overview

Alternatively, other applications can benefit from a shift right strategy, in which some test steps are transferred from final test and burn-in toward SLT, especially as SLT becomes more pervasive in manufacturing test.

SLT mimics in a manufacturing test environment the real-world operating conditions of the device under test, as described in a September 2020 GO SEMI & BEYOND article. In SLT, the device under test interacts with its mission-mode software and communicates with peripheral devices including power-management ICs (PMICs), DRAMs, and high-speed interfaces including USB or PCIe gen 4. Originally focused primarily on the memory and storage market during early silicon bring-up, SLT has expanded to include test of high-end processors and systems on chips (SoCs) used in computing, mobile, and automotive markets as well.

In addition to expanding to more markets, SLT is increasingly being applied to 100% of manufactured parts—not just samples. 100% SLT opens the door for a shift right of many test functions from final test to an enhanced SLT stage. This shift may also result in a lower overall cost of test.

High-speed interface test

One opportunity for the shift right of test content from final test to enhanced SLT involves connectivity and the test of high-speed I/O, but high-speed I/O tests bring about key challenges. In mission mode, a device will likely be soldered to a printed-circuit board close to its peripheral circuitry or inserted into an OEM socket on a computer motherboard. Neither is possible in the manufacturing test environment of SLT.

In SLT, connectivity and signal degradation problems—not defective devices—cause significant first-pass yield problems, seriously compromising throughput due to retest.

What’s needed is a high-performance, high-durability test socket for use in SLT that provides an optimized, tuned interconnect between the chip under test and its peripheral circuitry. To that end, Advantest in January 2020 acquired Essai, a supplier of semiconductor final-test and SLT test sockets (Figure 2) and thermal-control units. Essai possesses the expertise to design and manufacture the sockets with ever smaller pitches and ever higher electrical and thermal performance to address the final-test and SLT needs for successive generations of chips. These sockets permit at-speed test of high-speed interfaces at SLT, thereby enabling full-speed system level testing.


Figure 2. A test socket suitable for SLT provides mechanical durability while supporting an optimized signal path from the device under test to its peripheral components.

In addition, the socketed SLT motherboard enables a more native environment configuration for the device under test and better represents real-world conditions than does a typical ATE final test insertion, where propagation delays related to the path from device through the socket and load board and finally to the instrument must be taken into account.

Thermal test

Almost all of Advantest’s SLT customers are testing device behaviors at different temperatures at some point in the test flow, and most, if not all, of these tests can be shifted right to the SLT environment. 

An example in the automotive industry is the cold-boot requirement to ensure that vehicle electronics will boot up on an Alaskan winter morning. 

SLT can exercise a device at high temperatures, too. Many devices have temperature sensors, which may trigger a processor at a certain temperature to communicate with a PMIC to initiate a low-power operating mode until the temperature returns to normal.

Testing across temperature ranges presents its own challenges. For example, when you subject the device to different temperatures you are also subjecting the interconnect to different temperatures, leading to potential failures due to expansion and contraction. One solution is to get the device to temperature while leaving the rest of the SLT environment at as neutral a temperature as possible. Further, with heterogeneous integration, a substrate which may be as large as 100 mm on a side may accommodate multiple die, each with its own thermal response and challenge. Such a package might require topside contact by a thermal interposer that maintains temperature setpoints within different zones, all within that same package.


Finally, burn-in is a common test insertion for both automotive and high-performance compute devices. SLT test times extend from less than a minute to tens of minutes, and burn-in times extend from tens of minutes to hours. Given that the burn-in and SLT test insertions require some common thermal stress infrastructure, Advantest can enable the automation of combining SLT and burn-in in a common test cell. With some customers exploring high-speed I/O test during burn-in, burn-in can offer another opportunity to shift test content right.


Ultimately, in addition to its role mimicking the device under test’s mission mode, SLT is an opportunity to shift test content right. What it is not is an opportunity to completely replace other test steps. There will always be a need for final test, covering at a minimum short/open test to find assembly defects and performing multi-die communications checks and/or parametric measurements. On the other hand, the SLT test often includes creative interconnect solutions to high-speed memory, which require a test environment that would be impossible on an ATE system.

Committing to SLT for 100% of devices is a big step for companies to take, but once they do so they find that they can simplify final test by reducing test redundancy while continuing to ensure, and potentially enhance, the level of quality. Advantest serves the entire semiconductor manufacturing test space, from wafer probe to SLT. Advantest engineers stand ready to work with customers to determine the optimum deployment of test resources for their specific applications.


  1. Berry, Davette, et al., “Holistic approach to test coverage across Final Test, Burn In, and System Level Test,” TestConX, Mesa, AZ, March 3-6, 2019.
  1. Armstrong, Dave, “Heterogeneous integration prompts test content to ‘shift left,’” Chip Scale Review, January-February 2021, p. 7.
  2. Pizza, Fabio, “System-Level Test Methodologies Take Center Stage,” GO SEMI & BEYOND, September 27, 2020.
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Driving Toward Predictive Analytics with Dynamic Parametric Test

By Alan Hart, Senior Director, Applied Research, Technology & Venture, Advantest America, Inc.

The foundation of parametric test within semiconductor manufacturing is its usefulness in determining that wafers have been fabricated properly. Foundries use parametric test results to help verify that wafers can be delivered to a customer. For IDMs, the test determines whether the wafers can be sent on for sorting. Usually inserted into the semiconductor manufacturing flow during wafer fabrication at both the pre- and post-metal phases (as shown in Figure 1), parametric test has traditionally been used to check both transistor fabrication and metal layer interconnection, providing inputs to statistical process control (SPC) tools.

Figure 1. In the manufacturing flow, parametric test is typically inserted pre- and post-metallization, as indicated in blue above.

Measured data generated from the parametric tests is assessed and entered into a database, generating a report for an engineer to review. If an anomaly is highlighted, the engineer then orders the lot to be called back for retesting. This process typically takes a day or two, adding to the length and cost of the manufacturing cycle.

Dynamic parametric test (DPT), on the other hand, removes this review/retest loop by triggering immediate action upon measurement of an anomalous data point, based on the user’s predetermined parameters. This action takes place instantaneously, while the wafer is still on the tester – no reprogramming is required. Essentially, DPT elaborates on SPC techniques to establish these triggers, automating a process that, previously, would have required human intervention.

DPT drivers

The primary driver for implementing DPT techniques is the increasingly tight limitations created by shrinking process nodes. Today, 7nm and 5nm devices are in development (and the first 2nm process was recently announced). This translates to fabrication of leading-edge chips that comprise billions of transistors, whose features are separated by just a handful of silicon molecules. Testing billions of transistors individually is impractical, making parametric test vital for capturing statistics that reveal how the process went and help predict how well the circuit will perform. As devices get smaller and smaller, it becomes increasingly challenging to capture enough statistics to yield meaningful results, thus a greater volume of parametric tests are being applied in the assessment of wafer process quality.

DPT accelerates time-to-problem-solving, and hence, time-to-market, by enabling the parametric test system to instantly initiate data exploration based on customer-defined programming. By affording a deeper understanding of parametric deviations, it allows the user to program detailed characterizations for key devices, and to execute custom test flows based on real-time statistics or other user-defined criteria. As noted earlier, it adds automation to the engineering function – in essence, creating virtual engineering staff that can immediately analyze and debug unexpected results, or optimize test flow for tester utilization.

Advantest’s approach to DPT

Traditional parametric test looks at historical data to see what happened (descriptive analytics). Today, the process is evolving to capture additional data, allowing us to understand why it happened (diagnostic analytics). Going forward, the data will be correlated with future test results, enabling us to predict what will happen (predictive analytics). Predictive analytics, a key objective of Industry 4.0, enables corrective actions earlier in the manufacturing flow, as well as faster extraction of potential root-causes of deviations. Thus, by beginning to connect all the manufacturing steps shown in Figure 1, we can help wafer fabs and foundries begin to reap downstream benefits.

The goal is to be able to understand not only how well the circuit will yield at functional test, but also to predict its reliability when in use in its final application. For example, having one’s mobile phone fail is frustrating, but if it fails when you’re in your car and you need the GPS, or an emergency situation arises and you can’t call for help, the result could be disastrous.

Advantest’s Dynamic Parametric Test (DPT) software is a data-analytics enhancement to the V93000 SMU8 parametric test system, built on PDF Exensio® software from PDF Solutions. Together, Advantest and PDF Solutions have built a focused solution for parametric test that programs human decisions and actions into the tester to add real-time intelligence into the parametric test cell. Users implement DPT to immediately apply modified testing, both test algorithms and die map topology, allowing them to gain greater insight into the causes of unexpected results and to improve the efficiency of the test cell.

Figure 2 illustrates how the two systems work together. The DPT solution includes modifications to both the V93000 SMU8 system software and the Exensio data analytics platform. The solution is integrated into the V93000 SMU8 and into the Exensio server that manages the rules engine. Using customer-created rules, the software evaluates the incoming data from the tester, determines any necessary modifications to the test flow and/or test algorithms, and communicates them back to the tester, which then executes the new recipe. All of this happens instantly, in real time.

Figure 2. The Advantest V93000 Dynamic Parametric Test (DPT) system powered by PDF Exensio® DPT. The V93000 measures data and, via the event data log (EDL) stream, sends it to the Exensio software, which evaluates the data and immediately transmits any adaptive actions back to the test system to run the revised recipe.

No pre-programmed instructions are included in the DPT solution. The customer defines rules and models based on their own historical data and manufacturing requirements, which the system uses to look for anomalies and automatically trigger appropriate actions as the tests are run. The system identifies three basic types of triggers:

  • A value that deviates from historical results;
  • A statistical computation based on historical results from wafers/lots/time; or
  • Statistical trends based on historical results from wafers/lots/time.

The rules that define these triggers and their parameters are set up through a simple user interface, using test algorithms already available in the customer’s test library, and are applied either at the end of the die location test or the end of the wafer test (see Figure 3).

Figure 3. The DPT solution can apply the rules engine at the end of a die-location test or at the end of a wafer test. New data in the modified test flow is automatically collected, without requiring wafer reloading or engineering review.

Real-world example

The ways in which the system can be deployed are limited only by customer needs. As an example, Figure 4 shows a use case involving diode test, checking the forward voltage (Vd) necessary for a 100nA of current to flow through the diode. The spot measurements are distributed across the wafer, as a representative sample provides a good indication of how the entire wafer behaves. When a bad data point is discovered, the system might automatically switch from a spot measurement to a sweep measurement, adding more die locations, to determine whether the cause is a device point defect or a general fabrication problem.

In Figure 4a, the DPT run flagged an outlier device that returned an out-of-spec result. As Figure 4b illustrates, this then automatically triggered a deeper, five-point sweep measurement around the location of the faulty diode, which revealed further outliers in that region. Figure 4c condenses the sweep results, plotting the sweeps to determine what caused the two parallel lines to appear. In this case, the slope shows normal diode behavior, with no device leakage. The problem is thus determined to be a problem with the bad diodes’ saturation current (Is).

The system’s further calculations reveal that Is is only modified by p-n junction area (via photolithography) or by dopant density in the anode or cathode. Knowing the potential contributors of the saturation current are physical area and impurity concentration leads to two different potential root-causes. The engineer can then look at the topological pattern, which, in this case, suggests that the problem was in either a photolithographic or etch step, likely from a single multi-die reticle exposure. Thus, in less than a second of automatic additional testing, DPT has provided the engineer with an augmented data set for quick problem resolution.

The system can detect virtually any type of problem created during the manufacturing process, including back-end probe testing. On most parametric test floors, continuity test failures due to failing probe contact are not uncommon. When a continuity test fails, DPT performs further tests to determine if the problem is actually a defective die location or a probe needle that needs to be cleaned or repaired.

Once DPT validates that previously good die are now failing, it automatically performs a wafer probe card clean/polish step. It then can explore a wider topological region, automatically adding die locations to determine where the continuity problem occurred. If the error was caused by a dirty probe needle, which is often the case, retesting the last failed die along with additional die nearby will confirm that the problem was fixed. Again, DPT saves time and money by cleaning probes at just the right time, prolonging their use, and preventing a pause in the fabrication process.

The future: intelligent DPT

As mentioned earlier, the ultimate goal of DPT is to utilize machine learning to make the process measurement results truly predictive, allowing parametric test to estimate wafers’ functional test yield as many days or weeks before they reach that step. With this type of forecast in hand, chipmakers could potentially alter the subsequent test plans and correct process deviations much sooner.

Looking again the manufacturing flow diagram, we see that, with the V93000-Exensio DPT solution, data becomes more valuable at each downstream step. As Figure 5 shows, the parametric test dataset can now be used to forecast functional test yield, days or weeks ahead of the wafers reaching functional probe test, accelerating reaction time to process anomalies.

Figure 5. Using DPT techniques feeds forward upstream manufacturing process data to optimize downstream testing.

The DPT solution is part of a broader manufacturing tool set that will provide greater value from data already being collecting or can automatically add to the dataset. In future versions, interconnecting data from wafer fab through package test will provide insights using other tools in the Advantest Cloud Solutions portfolio to accelerate manufacturing response time.

To learn more about the Advantest V93000/SMU8 + PDF Exensio Dynamic Parametric Test solution, plan to attend the 2021 International Virtual VOICE Developer Conference, June 21-23. For more information and to register, visit

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