New Power-Supply Card Targets High-Voltage PMIC Test

By Toni Dirscherl, Business Lead, Power/Analog/Control, Advantest Europe

The electronics industry is seeing a move toward higher voltages and currents to deliver sufficient supply and charging power in products ranging from handheld cellphones and tablets to workstations. This trend is evidenced in examples such as the many USB power-delivery (PD) profiles with ratings ranging from 10W (5V at 2A for USB PD 3.0 profile 1) up to 100W (5V at 2A, 12V at 5A, and 20V at 5A up to the 100W limit for profile 5). In addition to higher power levels, today’s consumer products are exhibiting an increasing number of voltage domains, and they require power-management integrated circuits (PMICs) to manage the various voltage levels required for battery charging and other functionalities. The PMICs, in turn, present test challenges that ATE systems tailored for mostly digital devices cannot address due to missing high-voltage sources.

Universal VI instrument

To meet these challenges with a cost-efficient test system, Advantest has added a new card to its Extended Power Supply (XPS) Series for the V93000 EXA Scale™ SoC test platform. The new DC Scale XPS128+HV universal voltage-current (VI) instrument combines a high channel count (128 channels per card) with per-channel voltage and current ranges of up to 24V and up to 1A, creating a test solution that efficiently addresses the test requirements for high-voltage devices such as PMICs. The complete card consists of four 32-channel sub-modules with a test-processor-per-pin architecture (Figure 1).

Figure 1. XPS128+HV assembly (left) and 32-channel sub-module (right).

The XPS128+HV provides full channel compatibility with the low-voltage 256-channel XPS256 card successfully introduced to the market in 2020. The XPS128+HV can cover the same applications in the low-voltage domain as an XPS256, but the XPS128+HV seamlessly extends a system configuration to cover additional high-voltage needs, enabling efficient, highly parallel test of power-management devices with enhanced capability for high-voltage applications.

Figure 2 shows the operating IV characteristics of both cards. The region outlined in green represents the XPS256, which operates from -2.5V to +7V at currents up to 1A per channel. All three regions represent the XPS128+HV card. In addition to the green area of the XPS256, the XPS128+HV can operate from -10V to +15V at 250mA (dark blue outline) and from -1V to +24V at 150mA (light-blue outline).

Figure 2. XPS128+HV operating regions.

As shown in Figure 3, the XPS128+HV switches seamlessly between the -2.5V to +7V, -1V to +24V, and -10V to +15V ranges.

Figure 3. XPS128+HV seamlessly switching between ranges.

Signal quality and accuracy

To ensure signal quality and high accuracy, both water-cooled XPS cards include Advantest’s new Xtreme RegulationTM digital control loop, which can flexibly adapt to changing load conditions. Xtreme Regulation also supports programmable voltage and current slew rate and bandwidth settings (Figure 4) to provide an optimum solution for capacitive, resistive, or inductive loads. The programmable slew-rate function avoids excessive currents and noise during voltage ramps, eliminating current spikes during the initial charge of a capacitor and eliminating voltage noise from stray inductance.

Figure 4. Illustration of the XPS128+HV adjustable bandwidth capability on a 24-V channel.

The cards also include arbitrary-waveform-generation (AWG) and digitizer functions with a 2MS/s sample rate and 18-bit resolution for simultaneous voltage and current sampling. The AWG capability enables generation of current ramps on individual or ganged channels to perform threshold searches and other test methodologies.

Voltage and current modes

The core of the XPS256 and XPS128+HV is a digitally regulated VI source that can seamlessly change operating modes from a force-voltage mode to a force- or sink-current mode—often a requirement for testing power-management components such as low-dropout (LDO) or DC/DC regulators. For example, the seamless mode changes enable the cards to execute the fast test sequences necessary to perform DC/DC and LDO regulation tests and IDDQ current measurements while minimizing test times. 

In addition, the XPS128+HV provides seamless mode switching with no limitations related to transitioning between its high-voltage and low-voltage ranges. The card’s sequencer-controlled range-change capability allows extremely fast, deterministic test times without signal spikes that could harm a device under test (DUT).

The XPS card family delivers an extremely high force and measurement accuracy, often required for precise device trimming and for achieving high yields. Voltage accuracy is better than ±150 µV with a 10-µV resolution, while current accuracy is better than ±50 nA with a 100-pA resolution. 

Protective features

The XPS128+HV and XPS256 both offer several protection features. All channels are protected against external exposure of ±80V. The VI source features a patented fast current-clamp capability to protect load-board components, probe-card needles, and DUT sockets in case of a DUT short circuit, limiting inrush currents within less than 2 µs until the programmed clamp value is applied (shown in Figure 5). 

Figure 5. XPS128+HV current-limit response to simulated DUT short circuit.

To further provide probe-needle protection, the XPS cards perform simultaneous current and voltage profiling across the entire test flow to identify critical conditions such as power hot spots that could lead to damage. This background profiling occurs at 2MS/s. In addition, inline Vdrop monitoring measures the contact resistance for each channel to facilitate adaptive needle cleaning and to help schedule preventative maintenance. The profiling and monitoring offer sophisticated oscilloscope-like triggering capabilities (pre-trigger, post-trigger, and center-trigger) and impose zero overhead, uploading only on demand or upon a programmable alarm condition. Profiling can be seamlessly enabled and disabled without test-program modifications.

Multiple-card systems

The XPS series and other EXA Scale cards can be mixed and matched in a single test system. In a typical application, a V93000 test head might include PS5000 cards for digital I/O test and basic analog and mixed-signal test, a Wave Scale Mixed-Signal High-Speed (WSMX HS) card for noise evaluation and transient analysis, a utility card to supply and control load-board components, an XPS256 card to test low-voltage DC/DC converters and regulators, and an XPS128+HV card to test the high-voltage functionality of USB PD circuits and rapid chargers and to provide high-voltage screening. Both XPS cards allow flexible ganging of channels within each card and across cards without any impact on regulation performance. Ganging enables a combination of multiple channels to provide the current levels needed to test DC/DC converters that require multiple-ampere load currents.

Finally, in addition to PMIC testing, the new XPS128+HV can act as a standard power supply for high-performance-computing and automotive test applications. It can also be used for microcontroller (MCU) test, and it can generate high-voltage pulses for MCU flash programming.

Conclusion

Chipmakers increasingly need to perform multisite parallel test of PMICs that feature multiple voltage domains, and they require a power-supply card with a high channel count, combined with flexibility in voltage and current ranges. With its current rating of up to 1A and voltage rating of up to 24V, Advantest’s new DC Scale XPS128+HV instrument will enable chipmakers to configure a cost-efficient, large-pin-count ATE system with many power VI channels that can test high-current as well as high-voltage components while giving them the flexibility to gang multiple channels, meeting high-current needs at all voltage levels. Having already been implemented at several customer sites, the XPS128+HV VI is now available to the global market.

Innovative Memory Test Cell Leverages Scalable Parallelism and Compact Footprint for Final Test

By Zain Abadin, Sr. Director, Device Interface and Handling, and Masahito Kondo, Integrated Test Cell Solution Lead, Advantest

Products ranging from datacenter servers to automobiles require more and faster memory ICs, which must be thoroughly yet cost-effectively tested. As these chips evolve to provide ever higher levels of performance and quality, they are placing increasing demands on the test floor. An effective test solution must meet final-test requirements presented by the increasing bit densities, the power consumption, and the faster interface speeds of evolving memory devices. The solution will include automated test equipment (ATE) as well as a test handler that conveys devices under test to the ATE, establishes the proper test temperature, and sorts tested devices into bins according to their pass/fail status.

An effective approach to memory test requires a shift away from the memory-test paradigm that has dominated test floors for the past two decades. ATE and test handler companies have regularly increased parallelism, but each doubling in device capacity has been accompanied by a double-digit increase in test-system size. A way forward beyond 512 devices under test (DUTs) in parallel requires thinking beyond the handler or ATE individually to consider the configuration and performance of the entire test cell. Key points to address include the impact of system downtime; the effect of a big, heavy test cell and its footprint; and the test complexity that results from device variation and requirements for testing at multiple temperatures.

A successful memory-test-cell concept will maximize productivity while controlling cost of test through several features:

• Scalability would enable customers to configure their test cells based on current test requirements while retaining the ability to scale up when necessary.
• A single test cell would support efficient device evaluation at the R&D stage while offering the flexibility to be repurposed for production.
• At any level of scalability, the test cell would efficiently utilize floor space and optimize overall operating efficiency.
• Innovative software would apply artificial intelligence (AI) processing and analysis for tracking handler health and scheduling preventive maintenance. 
• For installations with more than one test cell, independent asynchronous test-cell operation would allow partial production test to continue even during maintenance on one cell.

Fully integrated test cell’s compact design saves floor space 

Advantest is now offering these features in a new minimal-footprint memory-test-cell family called inteXcell. The inteXcell infrastructure currently integrates T5835 memory tester modules, which incorporate full testing functionality for any memory ICs with operating speeds to 5.4Gbps, including next-generation memories ranging from NAND flash devices to DDR-DRAM and LPDDR-DRAM in BGA, CSP, QFP, and other packages. Throughput can reach 36,500 DUTs per hour.

TC5835 features include an enhanced programmable power supply to assist with testing advanced mobile memories, a real-time DQS vs. DQ (strobe vs. data) function to improve yield, a timing training function that is indispensable for high-speed memory tests, and test time reduction and defect-analysis functions based on various device data patterns. In addition to working with the TC5835, the inteXcell platform is designed to work with future memory-test solutions as well.

The inteXcell tester section consists of three units (Figure 1). The first, the AC rack, operates on 220VAC and delivers power to the test cell. Second, the server rack implements the system-controller, test-processor, and handler-controller functions. Third, as many as four test heads can test up to 1,536 devices in parallel. These three units have been designed to fit together into compact test configurations, eliminating the wasted space that can result when trying to integrate separately developed test-cell units. Consequently, inteXcell occupies one-third the floor space a conventional test cell would require.

Figure 1. The inteXcell tester section comprises an AC rack, a server rack, and up to four test heads.

From engineering to mass production

With inteXcell, ICs can be tested on the same platform from R&D through mass production. Figure 2 shows the scalable parallelism that inteXcell deployments can achieve. At the right, a base inteXcell can test 384 devices in parallel for initial engineering work. That cell can subsequently be repurposed for production. As production volumes increase, inteXcell’s scalable parallelism enables the addition of another test cell, providing a total test capacity of 768 devices in parallel. Moving from right to left in Figure 2, the addition of a third inteXcell brings capacity to 1,152 devices in parallel, while adding a fourth brings total capacity to 1,536 devices in parallel.

Figure 2. The inteXcell’s scalable parallelism provides flexibility for customers.

Reducing downtime

The inteXcell handler unit incorporates a new, compact chamber structure to provide an efficient and highly accurate thermal-test environment over an operating temperature range of -40°C to 125°C or, optionally, from -55 to 150°C.  New functions such as an automatic position correction capability and a one-touch type replacement kit also improve maintainability and reduce downtime.

In addition, new HM360 status-monitoring software comprehensively manages maintenance and temperature data for the handler unit, making it possible to develop predictive maintenance notifications using AI analysis. Sensors might detect, for example, that a handler pick-and-place mechanism is not achieving optimum vacuum levels. By monitoring deterioration in the vacuum performance, an AI algorithm could determine the optimum time to schedule maintenance. As illustrated on the far left of Figure 2, in a four-cell installation, production can continue at 75% capacity when one cell is taken offline for maintenance.

Minimizing need for operator intervention 

The production efficiency of the test process is further improved by the optimization of the test cell’s automated guided vehicle (AGV) or overhead hoist transport (OHT) function, which minimizes operator intervention. As shown in Figure 3a, a traditional flow involves obtaining untested devices from the virgin-device lot stock area and conveying them to a high-temperature test stage. The output of this stage will be either a failed device or one that requires further test. In the latter case, the device is conveyed to the cold test stage. The output will be either a failed device or a good device that has passed both hot and cold tests. As Figure 3a illustrates, this process involves eight operator access points requiring a complex scheduler/dispatcher.

(a)

(b)

Figure 3. Whereas a traditional test cell requires eight operator accesses for a two-temperature test, inteXcell reduces that number to four and eliminates the need for one lot stock area.

In contrast, inteXcell simplifies the test flow by completing both hot and cold tests with one lot input, as shown in Figure 3b. This approach eliminates the need to establish and access a lot stock area for parts that have passed the hot test, cutting the number of operator access points to four.

Conclusion

Advantest’s inteXcell platform is the first fully integrated and unified test solution to combine broad test coverage with high-throughput handling in a highly flexible system architecture. The new test cells have a compact structure that enables up to 384 simultaneous measurements per cell while using only one-third of the floor space occupied by conventional test systems. inteXcell’s scalable parallelism enables customers to choose the test capacity they need. In addition, each cell employs an independent asynchronous testing capability and AI-based performance tracking, enabling inteXcell to be configured from one to four testers, resulting in high equipment utilization, and streamlined cell-based maintenance. A four-test-cell implementation can test up to 1,536 devices in parallel with high speed and high accuracy. The inteXcell platform is expected to begin shipping to customers in the second quarter of 2023.

A Customized Low-Cost Approach for S-Parameter Validation of ATE Test Fixtures

This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022.

By Zhenhua Chen, Senior Application Engineer, Advantest Europe

Device under test (DUT) fixtures for ATE system pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ball grid array (BGA)/socket measurement. These challenges are further highlighted by the unique issues faced individually by probing on the ATE side and on the DUT side of the test fixture.

Usually on the ATE side there are only two types of interconnect: coaxial connectors, which can be easily probed using the appropriate cable assembly; and spring pin vias, which are more complicated to probe. A spring pin cable assembly with a coaxial connector or a probe/adapter can be used. On the DUT side, the BGA ballout of the device (pitch/pin-out) presents the first challenge to probing at the socket. The second challenge is that including the socket in the measurement requires compressing the spring pins, elastomer, etc. in the socket. This can be achieved with a properly designed interposer.

The traditional approach to addressing these issues is to utilize a generic commercial probe station, with a pogo via adapter on the top side of the load board and BGA pad on the bottom side. These stations are very large and costly, and using them requires prior experience and expertise. On the other hand, to “MacGyver” a solution, the user would need to obtain an ATE test fixture mechanical interface and assemble it for manual use, then modify a standard spring pin ATE cable assembly by cutting off the unified pin connector and attaching individual coaxial SMA connectors. This so-called solution, while less cumbersome than a commercial probe station, is not practical for quick and easy implementation, as it is time- and labor-intensive and difficult to replicate.

Custom probing kit to the rescue

Advantest has developed a cost-effective solution to these challenges: our custom probing kit for V93000 DUT test fixtures that can be easily assembled and implemented as a desktop ATE test fixture. Figure 1a shows what the user receives in the kit, while Figure 1b shows additional parts needed and illustrates how the DUT board is positioned on the bracket. Figure 2 shows an example of a completed, installed assembly.

Figure 1. Advantest’s custom probing kit includes everything needed to build a cost-effective desktop V93000 ATE test fixture. [Board image courtesy of Infineon]

Figure 2. Advantest’s probing kit can be quickly and easily assembled and installed on the user’s desktop, as shown in this example, with cables that can connect to any instrument necessary. [Board image courtesy of Infineon]

Addressing the de-embedding challenge

The IEEE 370-2020 standard incorporates parameters for measuring DUT performance, recognizing the critical importance of the test fixture in this capacity. This includes de-embedding, which the standard defines as “the process of removing fixture effects from the measured S-parameters [scattering parameters].” ATE test fixture de-embedding is not trivial; the measurement reference location is critical for de-embedding to be successful. The de-embedding reference point needs to be a location with stable electromagnetic (EM) fields. The de-embedding software will always de-embed whatever data is provided, but this doesn’t automatically mean that the de-embedding is physically correct.

Several de-embedding technique options are available. For ATE PCB test fixtures, we suggest the 2X-Thru approach, which requires a de-embedding test structure and is supported by the 370-2020 IEEE standard. The 1X-Reflect approach requires a short or/and open, and is not supported by the 370-2020 IEEE standard. Figure 3 provides an example of successful de-embedding.

Figure 3. This de-embedding example utilized the 2X-Thru approach.

As Infineon product engineer Manfred Brueckl noted, “De-embedding ATE test fixtures is a challenge that has typically required cumbersome or costly solutions. With this probing kit, Advantest has created a much-needed way to address this challenge that is both space-saving and cost-effective.”

Conclusion

Measuring the ATE PCB test fixture is a critical step that can save the test engineer a great deal of time later during initial application turn-on. This is especially critical for applications where test fixture S-parameters are required for the de-embedding process. Different probing approaches are possible to address this challenge, but because of the specific mechanical design associated with an ATE platform, using a customized probing setup provides the best cost/capability trade-off. Advantest has developed this setup in a kit that is easily assembled and implemented to accommodate a user’s specific requirements.

References

Books

• Jose Moreira and Hubert Werkmann, “Automated Testing of High-Speed Interfaces,” 2nd Edition, Artech House 2016.
• Luc Martens, “High-Frequency Characterization of Electronic Packaging,” Kluwer Academic Publishers 1998.
• Scott A. Wartenberg, “RF Measurements of Die and Packages,” Artech House 2002.

Papers on Socket Probing

• Heidi Barnes et al., “Performance at the DUT: Techniques for Evaluating the Performance of an ATE System at the Device Under Test Socket,” DesignCon 2008
• Heidi Barnes et al., “Advances in ATE Fixture Performance and Socket Characterization for Multi-Gigabit Applications,“ DesignCon 2012.
• Jose Moreira, “Design of a High Bandwidth Interposer for Performance Evaluation of ATE Test Fixtures at the DUT Socket,” ATS 2012.

Papers on De-embedding

• Jose Moreira et al.,“DUT ATE Test Fixture S-Parameters Estimation using 1x-Reflect Methodology,” BITS China 2017.
• Heidi Barnes et al.,“Verifying the Accuracy of 2x-Thru De-Embedding for Unsymmetrical Test Fixtures,” EPEPS 2017.
• Heidi Barnes et al., “S-Parameter Measurement and Fixture De-Embedding Variation Across Multiple Teams, Equipment and De-Embedding Tools,” DesignCon 2019.
• Xiaoning Ye et al.,“Introduction to the IEEE P370 Standard and its Applications for High-Speed Interconnect Characterization,” DesignCon 2020.

Wave Scale RF8: Ready for Wi-Fi 7

By Jan Ermert, Product Marketing, Advantest Europe

Since Advantest launched the Wave Scale family of test cards for the V93000 system-on-chip (SoC) test platform five years ago, we have continually added new products and capabilities to the line, allowing us to address new, emerging test demands. The Wave Scale RF8 card addresses the test challenges associated with the forthcoming Wi-Fi 7 standard by providing the bandwidth needed in an industry-proven instrument. Wi-Fi 7 covers the (so far, for Wi-Fi) unused frequency range between 6 GHz and 7.125 GHz, using up to 4096-QAM modulation schemes and up to 320MHz channel bandwidth (see Figure 1).

Figure 1. Wi-Fi band ranges are shown here, including the 3x increase in bandwidth enabled by advanced Wi-Fi. 

Figure 2 shows the Wi-Fi standard roadmap. With anticipated Wi-Fi 7 certification just two years away, customers need to plan their testing strategy now, integrating Wi-Fi 7 ready technology so that it is already in place when they are ready to begin rolling out Wi-Fi 7-certified products.

Figure 2. Current Wi-Fi 7 standardization, certification and commercialization timelines. [Source: “IEEE 802.11be: Wi-Fi 7 Strikes Back,” IEEE Communications Magazine, Volume 59, Issue 4, April 2021] 

Wi-Fi 7 application drivers

Wi-Fi 7 is optimized to ensure the highest possible throughput and the lowest latency. This comes in handy not only for entertainment apps but also for enterprise users and for virtual reality (VR) and augmented reality (AR) implementations. To this end, Wi-Fi 7 includes improvement for the different layers of the Open Systems Interconnect (OSI) model. Specifically, we’re looking at the physical layer, which determines how the data is transmitted and organized. It also defines how we deal with all aspects of an RF interface with regard to sharing a finite amount of spectrum between many access points and end points.

Many of these aspects will be addressed by new capabilities within Wi-Fi 7 releases 1 and 2. One of the key features being improved on is the introduction of even wider channel bandwidths in the relatively new 6GHz band. Release 1 proposes 320MHz and smaller channel bandwidths with up to 4096 QAM modulation – a major challenge for measurement equipment that is addressed by our Wave Scale RF8 solution.

The tradeoff for the impending bandwidth improvement in Wi-Fi 7 is that some range or signal reach may be sacrificed. During the transmission of a Wi-Fi 7 data package, it is necessary to convert the bits and bytes within the lowest part of the OSI model, the physical layer, into a phase- and amplitude-modulated analog signal at high frequencies, which can then be transmitted over the air. For the receiver to be able to extract the digital information from the received analog signal, the noise created by the signal chain must not be interfering with the signal. A typical measurement that tests for this interference is EVM, which checks the error vector, or delta between the signal as it should be and the signal as it was received (see Figure 3). 

Within the modulation the bits are encoded by shifting a carrier frequency both in phase and amplitude in discrete steps. This is typically plotted as a grid with each point on the grid representing one possible modulation state. Each point also represents a symbol, a pattern of bits that is unique to this one spot. The amount of grid points determines how many bits can be transmitted with one symbol. With a 4096 QAM, as used in Wi-Fi 7, each symbol carries 12 bits.

The denser this grid becomes, the faster the bit transfer for the same bandwidth, or spectral efficiency of the modulation scheme. This, however, has the huge disadvantage, that any noise added to the signal might lead to misinterpretation of the received symbol. The denser the grid pattern, the higher the sensitivity for noise. For a 4096 QAM, the expectations regarding a receiver are set very high, which, in turn, means the same for the measurement equipment measuring the receiver. For Advantest, this means that in order to provide a margin that guarantees the test results to be reliable, our test equipment needs to be multiple decibels better in EVM measurements than the DUT, and we’re well prepared to meet this challenge.

Figure 3. Example of a 16 QAM modulation scheme (l), EVM explanation, and calculation (r)

The Wave Scale solution

Wave Scale RF8 can perform both highly parallel multisite and in-site parallel test, testing both the send and receive channels in a fraction of the time required using a traditional test flow. It can also perform high multisite testing using native ATE resources, all within the V93000 test head. The card offers multiple benefits for Wi-Fi 7 test – in addition to support for 320MHz 4096 QAM, these include best-in-class EVM performance, wide operating frequency (10MHz to 8GHz), and scalability for in-site parallelism, among others (Figure 4).

Figure 4. Wave Scale RF 8 delivers unmatched parallelism with best-in-class EVM performance for Wi-Fi 7 testing.

Due to Wave Scale RF’s flexible architecture, high-performance/ultra-low-noise signals are provided by a Precision Source card when needed. This provides for a better driver signal, further improving the EVM for Wi-Fi 7. Wave Scale RF8 features a source combiner that couples two of its four independent synthesizers, doubling the 160 MHz bandwidth to achieve 320 MHz on the stimulation side and thus enabling the card to perform Wi-Fi 7 testing (Figure 5).

Figure 5. Each of the card’s RF subsystems functions as an independent instrument for highly parallel processing, enabling all ports to achieve 320MHz. 

Implementing this solution requires no additional accessories, nor any additional components on the load board or special test head cabling. This means that for existing Wi-Fi 6/6E configurations, there is no change necessary if the load board components support the frequencies and bandwidths for Wi-Fi 7. Wave Scale RF8, together with the SmarTest8 ATE software, provides best in-class Wi-Fi 6E testing today and is ready to accommodate your Wi-Fi 7 DUTs as they are developed and readied for production. 

As the technical ATE leader in Wi-Fi test, Advantest is committed to continually staying ahead of the technology curve. We have a track record of developing elegant, easily integrated solutions that anticipate customers’ needs for Wi-Fi testing capabilities. By building a rock-solid platform with a dedicated RF instrument card that offers high performance and flexibility, we are already supporting future standards and will be ready for Wi-Fi 7 when you are! 

Industrial Solutions for Machine-Learning-Enabled Yield Optimization and Test

This article summarizes the content of a paper developed and presented by Advantest at ETS 2022.

By Sonny Banwari, Vice President, Advantest Cloud Solutions, and Matthias Sauer, Applied Research Project Manager, Advantest Europe

According to market research firm Gartner, Inc., in assessing the completion rate of data science projects, as well as the bottom-line value they generate for their companies, only between 15 and 20 percent of these projects are ever completed. Moreover, of those that do manage to reach completion, less than 10 percent of them generate value, according to feedback provided by corporate CEOs. The bottom line: less than 2 percent of data science projects ever get completed AND deliver value. How can this squandering of corporate investment and effort be alleviated? One way is through the use of advanced machine learning (ML) techniques.

However, implementing ML in online manufacturing test poses its own set of challenges. ML-based applications challenge traditional test flows and infrastructures, as they require:

• Large amounts of data, often through multiple insertions spread geographically across multiple continents and located at various corporate entities depending on the position in the value chain;
• A secure, scalable and integrated compute infrastructure based on open standards; and
• A dynamic test execution infrastructure.

Some of these properties actually conflict with traditional test setups, which results in non-standard test flows and creates extra work that impacts time to market and return on investment – and, notably, slows success and adoption of ML applications.

Repeatability and reproducibility are essential to test procedures, particularly for automotive and other markets that rely on standardization and a high degree of compatibility. This requires establishing more structured thinking around ML and its impact on test. Figure 1 illustrates an industry-ready ML lifecycle designed to bring data science to the test floor.

 Figure 1. The four key steps of an ACS-powered machine-learning lifecycle are shown here.

ACS enables the ML ecosystem

Advantest Cloud Solutions (ACS) is a highly secure scalable data platform enabling an open solution ecosystem that helps customers address the most pressing challenges of the Smart Manufacturing era. The open aspect of the ecosystem is essential, as it allows any company along the supply chain not only to use it but to add value, create partnerships, deploy their own solutions, etc. ACS provides the vital infrastructure piece, as well as a wide range of development offerings through the ACS Solution Store, while Advantest provides other software products and services that customers can purchase when they need supplemental services to augment or enhance their existing deployments. Let’s take a brief look at each of the four key steps of the ML lifecycle.

Problem exploration and understanding

The earlier users seek to identify problems in the manufacturing process, the more data they require. Early bad-die detection is a vital component of this effort, as predicting likely failures post-packaging can help to significantly reduce costs and improve quality in the packaging process. To achieve this requires large amounts of high-quality data. Figure 2 shows the traditional test flow without benefit of ML techniques at left. At right, our ACS technology assesses data gathered from prior insertions and correlates it to accurately predict problems, enabling the user to circumvent them by fixing problems at the root cause, thus preventing bad die from reaching downstream test insertions. This reduces not just the cost of test but also the cost of the materials and processing needed as chips travel through the three-month long manufacturing process across continents and companies.

Figure 2. Using Advantest ACS techniques, customers can omit bad die early in the test cycle to reduce packaging costs and improve quality.

Model engineering

Model engineering is a crucial step for implementing assessed business requirements and turning them into a data-driven ML application, either using a custom implementation or employing pre-defined solution from the ACS Solution Store.

To evaluate the “ACS Yield Optimization” Reference App described above, we compiled a real-world dataset containing more than 200 relevant rest results per die from probe test and multiple fail bins from final test.

Running ACS-driven data analytics on the compiled, de-duped data, using one device under test (DUT) ID per entry, the tool uses deep learning-based variable selection to determine the variables of greatest influence on yield. It then creates new probe test limits based on the distribution of this data, removing false passes and confirming yield improvement. In the aforementioned case, the result was a 5% improvement in yield, from 88% to 93%, which translated to six-digit savings per year in U.S. dollars.

Figure 3. ACS Yield Optimization uses deep learning to analyze and optimize variable, resulting in higher yields and significant cost savings.

Deployment and execution

This refers specifically to secure, high-performance test floor integration of ACS with traceable deployments, as noted in Figure 1. Advantest purposely designed our ACS suite of tools not only for optimal results, but also for ease of use. Figure 4 shows our ACS Edge™ core product, which includes the ACS Edge Server and ACS Container Hub.

ACS Edge is a high-performance, highly secure edge compute and analytics solution that enables ultra-fast algorithmic AI decision-making with millisecond latencies during test execution. It connects to the user’s test equipment via a private, high-speed encrypted link and uses the advanced container hub to run the user’s protected applications while protecting and keeping secure the user’s data and analytics.

Figure 4. Advantest ACS Edge and available extensions help customers easily and securely integrate ACS into their test flow, enabling them to realize the full benefits of its ML-enabled capabilities.

Monitoring and validation

For models to move from the lab to volume production, they must be monitored for any unexpected behaviors resulting from changes in the product design or the test environment. The effectiveness of an optimization must be validated using real-world scenarios in order for a data science project to reach completion and contribute to a company’s overall value.

Semiconductor production is highly influenced by process variations from die to die, wafer to wafer, or lot to lot, particularly at smaller process nodes with tighter geometries that afford less room for deviation. Thus, there is an inherent risk of “silent” model degradation of when a learned process characteristic changes, potentially impacting the quality of the model (yield, test time, device quality, test escapes, etc.) ACS employs a continuous learning loop with continuous monitoring, greatly reducing this risk so that models retain their integrity.

ACS Solution Store 

Another key piece of the ACS ecosystem that helps create a unified, repeatable workflow is our ACS Solution Store, which provides ease of access to ACS real-time data infrastructure solutions and software applications. This online platform enables customers to discover, purchase and securely deploy all available ACS solutions from Advantest and a broad spectrum of analytics ecosystem partners across the semiconductor lifecycle process. In addition, the ACS Solution Store enables application developers from these partner firms to publish, promote, distribute and manage their Advantest-certified apps.

This latest aspect of the ACS offerings is vital to maintain an open ecosystem, as it facilitates access to all ACS offerings for customers, as well as giving them and our partners the ability to develop and publish their own apps. This allows sharing of new capabilities and best practices so that the capabilities of our ACS technologies can be optimally leveraged across companies throughout the semiconductor ecosystem.

We continue to expand and evolve our Advantest Cloud Solutions to meet evolving customer demands. By putting ACS in place within their test environments, customers can ensure they’re armed and ready for the future of semiconductor test.

Engineering Test Station Facilitates Post-Silicon Validation

By Adir Zonta, Advantest

The semiconductor market is evolving, with devices becoming more complex as chip designers add cores and pursue 2.5D and 3D integration strategies. This complexity presents challenges extending from design and simulation through system-level test (SLT), where a device is exercised in mission mode, booting up an operating system and running end-user code, for example.

These challenges arise from the exploding volumes of test data that must be acquired and analyzed throughout the design and test process. In addition, chipmakers are increasing the number of new product introductions (NPIs) per year as they diversify their product portfolios.

The exploding data volumes and proliferating NPIs in turn are combining to increase the need for flexible test processes and equipment, and they are straining engineering teams and their facilities. 

Worst case, a company could be faced with building a new engineering facility, either next door to an existing one or in a remote location. 

Ideally, a company would find a way to increase its capacity without expanding its engineering facilities. The arrival of first silicon presents a particular pressure point, when companies must deploy teams of engineers to perform device bring-up, pattern generation, and characterization.  

Engineering test station

Advantest is addressing the needs of such customers by augmenting its V93000 EXA Scale SoC Test System lineup, which targets advanced digital ICs up to the exascale performance class while lowering cost of test and shortening time to market.

Advantest’s latest offering in the family is the V93000 EXA Scale EX Test Station—a state-of-the-art engineering platform for complex device bring-up that supports structural and functional test.

To enable a fourfold increase in tester capacity within the same engineering lab footprint, the EX Test Station fits under Advantest’s single-site M4171 automated handler, which brings automated device loading, unloading, and binning into the laboratory environment.

The handler features integrated active thermal control (ATC) over a -45 to +125°C range. ATC supports fast data collection and can improve temperature cycle testing throughput by 40% compared to manual thermal-control approaches. The handler also can include a camera to facilitate remote work and 24/7 availability. The total test-cell footprint measures 0.56 m by 0.82 m, allowing six test cells to fit comfortably within a 5-m by 5.5-m laboratory space (Figure 1).

Figure 1. Typical engineering layout of EX Test Stations with M4127 handlers.

To further save space, three, six, or nine EX units can share a single cooling unit. Furthermore, the tester, handler, and thermal-control unit form a highly automated combination to conveniently and quickly gather the high-volume data needed for today’s successful silicon bring-up activities without continual intervention by engineers. Recent experience with remote work has demonstrated its feasibility for test-engineering applications. Rather than having a complete team of engineers on site, a single operator can be available to provide hands-on assistance to address any issues observed by the engineers working remotely.

The EX Test Station employs Advantest’s Xtreme Link technology, designed specifically to provide high-speed optical data connections, embedded computing power, and card-to-card communications for ATE.

Although not intended for use in high-volume manufacturing (HVM), the EX Test Station does have full throughput capability and is therefore suitable for testing initial engineering batches efficiently. In addition, it helps to ensure seamless flow between the engineering and HVM environments. To ensure a smooth transition to Advantest’s V93000 production-test system with perfect correlation, the EX Test Station includes a V93000-compatible DUT board and uses V93000 SmarTest 8 software as well as V93000 instruments (Figure 2).

Figure 2. The EX Test Station with V93000 DUT interface and three universal slots.

Specifically, the EX Test Station accommodates up to three EXA Scale cards, including Advantest’s XPS256 Extended Power Supply (XPS) device power supply (DPS) card, which delivers 256 channels of power at current ratings in the thousands of amperes at voltages below 1 V.

In addition, the EX Test Station accepts the Pin Scale 5000 digital card, which achieves 5-Gb/s speeds and is designed to address the explosion of scan data volumes inherent in large digital designs.

The EX Test Station also works with members of Advantest’s Link Scale™ digital-channel-card family for the V93000, which enable software-based functional testing of advanced semiconductors. Link Scale cards also support USB/PCI Express (PCIe) scan testing and address testing challenges that these high-speed interfaces present. During test, the Link Scale cards communicate with the DUT through the USB or PCIe interfaces running in full protocol mode. This approach tests a device in its normal mode of operation using firmware and drivers similar to those in the target application—thereby adding System-Like-Test™ capabilities to V93000 EXA Scale systems, including the EX test station. System-Like-Test enables tests that might otherwise be applied at SLT to shift left to an ATE system.

The Link Scale cards also enable the reuse of pre-silicon functional tests by leveraging the Portable Test and Stimulus Standard (PSS), which is supported by major electronic design automation (EDA) tools and which significantly improves test quality and reduces time to market.

Finally, the EX Test Station accommodates a utility card and includes a module with 64 utility lines and a 5-V utility supply. (An external utility power supply is optional.)

The cost-optimized EX Test Station with engineering cart, integrated power supply, peripherals, and shared cooler helps control facility costs through its 4x improvement in engineering floor capacity and by reducing power requirements—it operates on single-phase, 200- to 230-V, 30-A power.

Conclusion

The drastic increase in test-data volume coupled with a proliferation of NPIs is spurring on an increasing demand for investment in engineering. Advantest’s EXA Scale EX Test Station represents a cost-effective optimized solution that performs structural and functional test to support the bring up, debugging, and characterization of complex digital devices. Combined with the M4171 handler, it forms a highly automated engineering test cell with remote-access capabilities. The complete test cell offers a fourfold increase in engineering-lab capacity without any increase in footprint while minimizing engineering costs and cutting time to market.