The Metaverse Matrix: Transforming Semiconductors with Digital Twins
Join us on “Advantest Talks Semi” as we explore the transformative impact of the industrial metaverse with Don Ong and his guest, Sanjeev Kumar.
Sanjeev Kumar is a Silicon Valley entrepreneur and advisor specializing in enterprise AI, data management, tech-bio, and industrial automation. With over seven years of investment experience, he has worked closely with early and mid-stage startups through venture capital (VC) firms and accelerators. Previously, Sanjeev held leadership roles at Informatica, BEA Systems, EMC, and Oracle, focusing on machine learning, data engineering, and enterprise software platforms. He also served as managing director of India R&D and GM for multiple products at BEA Systems and Informatica. Sanjeev holds an MS in computer science from Rutgers University and a BS from BITS, Pilani, India.
In this episode, we dive into how the industrial metaverse is reshaping semiconductor manufacturing, from digital twins optimizing production efficiency to real-time analytics driving smarter decision-making. Sanjeev shares insights on how AI, IoT, and advanced simulations are converging to revolutionize supply chains, predictive maintenance, and factory automation. We also discuss the role of edge computing and distributed security models in enabling seamless data exchange between physical and virtual environments.
From early digital modeling techniques to today’s persistent and immersive industrial metaverse, this conversation provides a comprehensive look at the evolution of these technologies and their future impact on semiconductor testing, design, and manufacturing.
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Advantest’s VOICE 2025 Draws Record Attendance in Austin, Texas
Advantest concluded a successful VOICE 2025 at the AT&T Conference Center in Austin, Texas. The event was held on May 12-14 and drew a record-high attendance of over 470 attendees, the majority of whom were Advantest customers and industry partners.
The VOICE 2025 committee received more than 200 abstract submissions from 39 global companies across 13 countries. Of those abstracts, 89 papers were presented over two days, the majority of which were written or co-authored by Advantest customers. The track listing featured a wide range of topics important to the automatic test equipment (ATE) industry, such as 5G/millimeter wave, high-performance computing (HPC), artificial intelligence (AI), test methodologies, as well as a new track covering automotive, power, analog, and mixed-signal.
This year’s event featured an exciting lineup of three keynote speakers: John Yi, Fellow at AMD; Andrew Yick, senior director of product and test engineering at Marvell Technology; and Roy Meade, executive director for strategic partnerships at the Texas Institute for Electronics.
In addition to the keynote presentations, attendees had the opportunity to engage with Advantest R&D engineers during the Technology Kiosk Showcase. The event also included “Talk with Experts” lunches, where participants could sit down with experts from Advantest and sponsoring companies to discuss a variety of topics, including silicon photonics, power consumption, thermal control, and silicon validation. Attendees enjoyed valuable networking time during evening events and scheduled breaks. Additionally, a Workshop Day was held on May 15, offering hands-on sessions that focused on advanced RF modulation and demodulation on the V93000 SoC Test System.
The VOICE Partner’s Expo took place throughout the event, enabling Advantest’s partners and sponsors to meet with attendees and exhibit their latest products and offerings. This year’s headline sponsors were Alliance ATE Consulting Group and ISE Labs/ASE Group.
Best Paper and Best Kiosk Awards
Attendees voted for the Best Paper and Best Kiosk awards using the VOICE mobile app. This year’s Best Paper awards were presented to Ritesh Mehta from NVIDIA for his paper titled “Predictive Test Selection for Silicon at System Level Using Machine Learning and Cloud Services,” and to Brian Buras, Keith Schaub, Constantinos Xanthopoulos, Yichuan Lu, and Navnath Raut from Advantest for their paper titled “Leveraging Generative AI for Domain-Specific Knowledge Retrieval and Interaction.”
Anik Mehta of Microsoft and Phil Brock of Advantest received an Honorable Mention for their paper, “Left-Shifting Functional Validation to Wafer Sort Test Methodologies.” Additionally, Michael Kozma, Juergen Sang, Alex Perlman, and Benny Wang from Advantest were given an Honorable Mention for their paper titled “Vmin to the Max: A New Approach to Single-Sequencer Run Searching Test Methodologies.” This year’s Best Kiosk award was won by Keith Schaub, Don Ong, and Nadine Schill from Advantest for their “Advantest Talks Semi” kiosk.
Visionary Award
This year’s Visionary Award was presented to Kar Leong, senior director of test engineering, Qualcomm. Recipients of the Visionary Award are honored for their significant and sustained contributions to VOICE over time. Leong has contributed papers to VOICE for the past nine years and won the award for Best Paper in 2012.
VOICE 2026
Thank you to everyone who joined us for VOICE 2025! VOICE 2026 will be held in Scottsdale, Arizona, at the Fairmount Scottsdale Princess on May 18-20. For more details, please go to: https://voice.advantest.com/.
Advantest Unveils SiConic™ Test Engineering: Unified, Scalable Bench Environment for Debug and Validation
In May, Advantest unveiled SiConic™ Test Engineering (TE), the newest addition to the SiConic™ family introduced in February 2025. SiConic TE offers test engineers the ability to bring up and validate structural and functional tests over high-speed I/O (HSIO) interfaces in a scalable bench environment, enabling earlier validation and debug without occupying valuable ATE systems.
SiConic Link flexibly connects to standard evaluation boards through functional interfaces like USB, PCIe, control interfaces, and GPIOs. This is the foundation for SiConic TE to enable test engineers to rapidly validate and debug design verification (DV) and design for test (DFT) content in SiConic’s unified environment on the bench.
Building on V93000 leadership in scan over USB or PCIe, SiConic’s unified environment brings native DV test content to test engineering without the error-prone and lengthy conversion and debug cycles typical for bring-up of advanced functional tests on ATE. These tests are required for high-quality test coverage in verification and test, enabling a productivity boost for the bench collaboration of DV, DFT and test engineering. SiConic TE accelerates time-to-quality for both V93000 as well as Advantest’s SLT and burn-in platforms with the ActivATE360™ suite of software tools.
Integrating seamlessly with SiConic Link hardware and the SmarTest 8 software platform, SiConic TE provides users with comprehensive access to functional HSIO links for enhanced throughput and rich trace capabilities during test execution. By enabling smoother handoffs between silicon validation (SV), DV and TE teams, SiConic TE fosters tighter cross-domain collaboration.
Through its unified test environment and shared ecosystem, SiConic TE improves the correlation between bench, ATE and SLT systems. The tool’s optimized engineering resources allow bring-up and debug to be offloaded from ATE to the bench, freeing up valuable tester capacity and enabling more effective scaling. In addition, tight integration with leading EDA partners enables cross-functional collaboration with DV and DFT teams, improving test content development and speeding first-silicon success.
According to G. Dan Hutcheson, vice chair, TechInsights, “Improving productivity at the R&D level is vital for design engineers. Advantest’s automated silicon validation approach would allow sign-off and test engineering to proceed concurrently using shared test data, helping ramp SoC designs more quickly, and shortening time-to-money, while ensuring design-to-system quality.”
Industry Support
Advantest developed SiConic TE in close collaboration with leading customers and EDA partners to ensure seamless integration into existing design and validation flows.
“Siemens EDA and Advantest have a long history of joint development on many DFT technologies, including Tessent Streaming Scan Network (SSN) and IJTAG,” added Ankur Gupta, senior vice president and general manager, Digital Design Creation Platform, Siemens EDA, Siemens Digital Industries Software. “Collaborating on Advantest SiConic and Tessent In-System Test strengthens this long-running collaboration and helps to provide our users with time-to-market improvements and higher productivity.”
“As the scale and complexity of chips continues to increase, new verification approaches are needed to shift verification cycles earlier and deliver silicon with higher quality,” said Tom De Schutter, senior vice president of product management at Synopsys. “Our collaboration with Advantest enables users to develop drivers for high-speed interfaces, validate SERDES and perform functional testing and structural testing through the combination of Advantest’s SiConic platform and Synopsys’ HAPS-100 platform, VC Portable Stimulus, TestMAX SF/SEQ and SLM HSAT IP solutions.”
More information:https://www.advantest.com/en/news/2025/20250508.html
