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Posted in Top Stories

SmartShell – A Unique Software Interface for Design and Production

By Shu Li, Business Development Manager, Advantest America and Michael Braun, Product Manager, Advantest Europe

Before device test can take place on automated test equipment (ATE), device-specific test programs need to be developed for the target device and test system. As part of this process, a large amount of digital test content (patterns) gets translated from EDA (design/simulation) to ATE (test) format and needs to be debugged and characterized on the target tester.

In the mixed-signal (MX) and radio-frequency (RF) domain, scripts in various languages (tcl, Python, LabView, etc.) are often used for device bring-up and characterization on bench instruments, using early device samples on an evaluation board, either before ATE test program development starts or sometimes in parallel.

These often interactive scripts are not natively applicable to the production test system, so ATE users have developed proprietary solutions to bridge the gap between ‘bench type’ engineering test and production test environments. This enables leveraging some of the early device learnings for volume testing, or simply running the same test scripts in the two very different environments.

Both digital pattern validation and MX/RF script execution or conversion to ATE have potential for improvement and standardization, which will benefit both time-to-market (TTM) and time-to-quality (TTQ). This article will provide further details for both areas.

Digital (DFT) pattern bring-up and validation

Test patterns for scan, built-in self-test (BIST), functional, or other digital tests are typically created by design or DFT engineers in their design/simulation (EDA) environment and then handed over to the test department, where they are converted to the native ATE pattern format and integrated into the production test program. As part of this process, all patterns need to be validated and characterized on the tester, to make sure that they work as intended and have enough margin to guarantee a stable production test.

This pattern bring-up and validation process can be very time consuming because initial pattern generation and bring-up/validation is typically done in two very different environments: design/DFT/simulation versus test engineering. The design or DFT engineer creates the test patterns, but it is the test engineer’s responsibility to convert and run them against the actual silicon. If they don’t work, the test engineer will produce a log file with failing cycles for the pattern at hand and send it to the designer, whose task is then to identify the root cause of the failures in the simulation environment and to re-generate a corrected test pattern as needed. The corrected pattern needs to be translated and validated on the tester again, going back and forth between design and test. Often, design/DFT and test engineering are isolated from each other, in two different locations, communicating by email or FTP. The test engineer will thus notify the DFT engineer of discovered errors, but the latter may not get around to re-simulating the test patterns immediately. As a result, the test development process will incur some delays. The majority of patterns may pass, but some tricky ones can take months of re-spins, which will not help with getting working products to market quickly. This traditionally manual process – offline pattern generation, conversion and download, then emailing feedback about errors – is painful and time consuming (Figure 1).

If there were a way to execute and validate the generated patterns directly from the DFT/simulation environment without going through the full circle of pattern translation and fail cycle collection for every minor change, it would benefit all parties involved and reduce the pattern bring-up cycle time.

 

Figure 1. The debugging process involves lengthy communication between design and test, requires significant learning, and is prone to errors, leading to lengthy cycle times.

 

Scripts for mixed-signal/RF ‘bench instrument’ test on ATE

Mixed-signal and RF testing involves, besides some digital resources to set up and control the device, additional analog and RF instrumentation. In a lab environment, these resources are benchtop instruments such as oscilloscopes, spectrum analyzers, waveform generators and other tools.On the bench, each test requires specific control scripts for both the device and the various lab instruments involved. On the ATE system, fully integrated hardware instruments are used and controlled by standardized software components that are part of a generic test program. Often, bench instruments have a higher precision for specific tasks but are not as universal as ATE resources and cannot reach nearly the same throughput as ATE can deliver. For volume data collection in characterization, significant effort must be made to reach high throughput for data collection from many devices in a reasonable amount of time. Leveraging an ATE to do some tasks that are normally done in the lab/bench environment will speed up this data collection significantly and help to smooth the transition between design/bench and ATE. In this context, it would be very helpful to have a solution that allows moving back and forth seamlessly between the lab/bench environment and the ATE, without the need to convert bench-type scripts into ATE ‘native’ test programs. Running the exact same script(s) on the bench AND on the ATE system would help to improve correlation and TTM, while leveraging knowledge from both environments.

Figure 2. Time to market is a major issue when dealing with scripting for mixed-signal/RF devices. Producing a working customer sample can take 9-12 months, depending on chip size, type, etc.

Building a unified interface to bridge between design and test

What’s needed to address these challenges is an easy-to-use client/server environment that simplifies the communication between design and test to enable smart debugging. Advantest has developed a software option for its V93000 system-on-chip (SoC) test system that provides such a solution.

The newly developed SmartShell is a software environment for digital pattern validation and native script execution on ATE. The interface links directly between the DFT/bench environment and the V93000 tester, without the need to convert patterns and scripts to the tester’s ‘native’ data format. This allows fast pattern bring-up and characterization, enabling DFT engineers to validate their patterns faster and designs to be characterized more efficiently before they are released to production on the V93000 system. The block diagram in Figure 3 illustrates the dataflow process.

Figure 3. SmartShell data flow, from pattern/script generation to ATE and back.

With this new tool, porting different test content is made easier and straightforward, giving designers the freedom to incorporate various tasks into their test program without having to think about how to port them to an ATE system. Those that work best for the device being developed will be converted when it comes to manufacturing.

Engineers in both design and test can use the tool. The DFT engineer can run a simple script instructing the tool to check a new pattern or to loop over a number of patterns while varying conditions like voltage or frequency. He or she can access the results directly from their environment, without having to learn the native formats and software environment of the test system. The test engineer can run scripts originally generated for a totally different environment, and then quickly compare ATE results with results from the bench instrumentation. The command interface controls functionality and execution, and allows the results to be viewed in the engineer’s preferred format (see Figure 4).

Figure 4. The software package features an interface that is easy to use for design and test engineers alike.

SmartShell’s key capabilities include:

  • On-the-fly control of tester resources for digital, mixed-signal, RF and DC measurements
  • Fast internal pattern conversion, execution, and back-propagation of results
  • Ease of programming using any command-based script language
  • Accommodates customized script language using a bridge to its standard set of commands
  • Auto-recording/generation of setups for early production to ensure reusability
  • Compatible with SmarTest 7 (DFT/pattern validation only) and SmarTest 8 (Scripting)

Summary

SmartShell represents a solution to bridge the gap between design and test, delivering capabilities for pattern validation and script execution that are beneficial regardless of company size or device type. Early validation can be done in a well-contained design or bench environment, without the need to ‘learn the tester.’ The highly programmable SmartShell interface for the V93000 allows experts to best utilize their individual skillsets to debug devices effectively and efficiently in a highly integrated manner. The tool significantly shortens the turnaround times for high-quality test patterns and scripts, enabling device makers to achieve both faster TTM and lower overall cost of test.

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Posted in Featured Products

W2BI’s New MLT1600 Device Test Automation Platform Addresses LTE, GSM and WCDMA Capabilities for the Burgeoning IoT and Smartphone Markets

W2BI, an Advantest Group company and a global leader in wireless device test automation products for the world’s top wireless operators, suppliers and labs, has introduced the MLT1600 cloud-enabled, device test automation tester as the newest member of its Micro Line Tester portfolio. The MLT1600 addresses the testing challenges of IoT products across multiple cellular radio technologies – such as GSM, WCDMA and LTE – with a 70-MHz to 6-GHz frequency range. With its portable design and small footprint, the MLT1600 leverages W2BI’s existing cloud-based test management platform to acquire on-demand test cases and publish test results as required across all test parameters.

During Verizon’s Test Fest in Bridgewater, N.J., W2BI demonstrated the MLT1600 with multiple-use case scenarios, including device connectivity, VoLTE, IMS roaming, data performance, UICC and more. The system software includes commercial-grade eNodeB, EPC, IMS and built-in Web-App-FTP servers to provide end-to-end network emulation in support of automated testing to accelerate time to market with increased capacity.

As mobile devices continue to grow in number, they are becoming increasingly sophisticated and able to perform complex functions across all industries and consumer markets. Cellular networks, which span the globe with standardized mobile access and interoperability, are seeing a proliferation of IoT devices and applications. To ensure that devices and services remain highly reliable, wireless operators around the world need to ensure that new technologies meet the demands and the security requirements of the expanding IoT ecosystem.

To support this growth, W2BI is simplifying the testing process by offering MLT products that use multi-level intuitive reporting to enable rapid troubleshooting and root cause analysis of test failures. The results can be published over the cloud to allow remote log analysis. In addition, MLT test equipment automation products are expandable, easy to use and offer shorter test cycles with more comprehensive analysis.

W2BI is continually pursuing ways of lowering the cost of testing and making the technology accessible to all groups across the mobile ecosystem. The company is constantly expanding their test automation scripts that support mobile operator-specific and industry standards-based test specifications, such as 3GPP, Global Certification Forum and CTIA, to accelerate and simplify the testing process.

 

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Posted in Upcoming Events

Advantest’s VOICE 2018 Call for Papers Ends Nov. 17

VOICE, the annual Advantest Developer Conference, has issued an international call for papers for the 2018 event focusing on innovative test solutions for system-on-chip (SoC) and memory semiconductor devices, handler solutions, best practices and other hot topics. Paper submissions will be accepted through November 17, 2017.VOICE, the annual Advantest Developer Conference, has issued an international call for papers for the 2018 event focusing on innovative test solutions for system-on-chip (SoC) and memory semiconductor devices, handler solutions, best practices and other hot topics. Paper submissions will be accepted through November 17, 2017.

In 2018, VOICE will return to the host cities of San Diego, Calif. and Hsinchu, Taiwan on May 15-16 and on May 23, respectively, under the unifying theme “Measure the Connected World… and Everything in ItSM.”

Comprehensive learning and networking opportunities including technical presentations, a partners’ exposition and social gatherings continue to be the cornerstone of the VOICE program. Additionally, attendees can connect with Advantest product experts during the expanded Technology Kiosk Showcase at both conference locations. For the first time, VOICE will include a Best Kiosk Award that will be voted on by attendees.

Advantest’s VOICE 2018 call for papers focuses on six technology tracks:

  • Device/System Level Test — specific devices and system level test; MIMO; mmWave; next-generation embedded processors; broadband fiber to the home; autonomous vehicles IC test; multi-chip system-in-package
  • Internet of Things (IoT) — IoT enabling technologies; mobility, 5G, wireless, RF, wearables; smart cities/homes; sensors; tactile internet
  • Test Methodologies — supporting standards and protocols; solutions for the latest testing challenges
  • Hardware & Software Design Integration — utilizing the latest hardware or software features; test cells; new test system enhancements
  • Optimizing Productivity — cost of test; throughput; time-to-market; semiconductor “supercycle”
  • Hot Topics — new market drivers and future trends; artificial intelligence; smart data innovation; secure ID and cyber security; secure cloud; video streaming/telepresence

Unique sponsorship opportunities are also available for both locations. Please contact Amy Gold at amy.gold@advantest.com for more details.

Hotel reservation information is already available on the VOICE website, and registration opens in January. Visit https://voice.advantest.com to learn more.

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Posted in Uncategorized

Advantest Taiwan CEO Guides with Balanced Leadership Approach

By GO SEMI & Beyond Staff

The subject of this issue’s Q&A is C.H. Wu, chairman, president and CEO of Advantest Taiwan. Mr. Wu has served in these roles since 2006, and in 2012, he was named an executive officer with Advantest Corporation. He holds a bachelor’s degree in electrical engineering from Taiwan’s Lunghwa University of Science and Technology and an MBA from Saginaw Valley State University in Michigan.

Q: You received your undergraduate degree in Taiwan, and your MBA in the U.S. How did you begin to develop your business acumen?

A: Growing up, many of my family were farmers, so I helped with farm work, such as rice seeding, weeding and husk drying. It was daunting to face those huge fields, but I soon realized that setting milestones and working steadily to completion is the best way to tackle any big job. This work ethic helped me to finish the farm work efficiently, and when I entered the job market, I continued to apply it to my efforts in the business world. I had trained myself to perform at a high level so that I could achieve excellent results in a timely manner.

Q: How did you come to join the semiconductor equipment industry?

A: A statement that has guided me in many of my life choices is “Know who you are and what you want.” After earning my degrees and working at big international firms such as Philips Electric and Motorola, I began to think about what mattered most to me in terms of moving forward in my career. I was familiar with the semiconductor industry, of course, and I chose to join Advantest Taiwan in 1990, just as the semiconductor equipment industry was beginning to boom. That decision opened up an exciting chapter in my life – one that has lasted more than two decades.

Q: What is your management philosophy?

A: I believe that task delegation must be balanced with ensuring cooperation and collaboration between company departments. For Advantest to remain successful over the long term, every member of the company must be invested at a personal level in helping sustain overall corporate growth. Our “2020 Project” cultivates in-house talents by inviting employees to propose, plan and implement innovative activities. We believe this program inspires technology advancements that benefit the company while reflecting Advantest’s core values and leadership position in the era of the Internet of Things.

We have implemented a number of projects in the last 25 years to recognize employees’ talents in different areas. Besides collaborating with academic institutions in skills development, we have combined our internal training program and job rotation mechanism to encourage employees to develop their strengths and make the most of their capabilities. A company’s success is not possible without each person’s individual contributions and unique talents. It’s therefore a leader’s responsibility to find ways to leverage the right people working in the right places doing the right things.

I also believe that career accomplishment isn’t the only measure of a person’s success. Good health, close friendships, and strong family relationships are all indispensable to a happy and well-balanced life.

Q: In what ways does Advantest differentiate itself from competitors?

A: I believe partnering with customers is absolutely essential. We must understand their challenges as well as they do in order to create a partnership that benefits each side. Just selling products won’t produce long-term relationships, and customers appreciate our efforts to ensure that we’re not just selling to them, but are helping them to achieve their long-term success goals.

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Posted in Top Stories

Inline Contact Resistance Solves Wafer Probing Challenges

By Dave Armstrong, Director of Business Development, Advantest America, Inc.

Testing is increasingly being conducted at the wafer level as well as at lower voltage levels, necessitating even greater test accuracy. Achieving this accuracy is often hampered by poor contact resistance (Cres). In this environment, conventional continuity tests – in which current is applied in parallel to all pins and per-pin diode voltage is measured to verify continuity between the tester and the internal die – are not adequate for determining yield limiting contact problem. Moreover, they have no value in determining potential issues with probe card degradation over time.

Probe cards often are subjected to offline electrical contact resistance measurements, but contact resistance grows as the probes become dirty. As wafer probing progresses, if one pin starts to make poor contact, the situation will worsen, resulting in a large quantity of potentially good parts being turned away. To prevent the impact of accumulated residue affecting probe and test quality, inline contact resistance is becoming essential. Similar to the shift toward inline process control that became industry-standard in the early 2000s, measuring contact resistance inline will serve to mitigate the problem of dirty or damaged probes, unlike continuity testing.

Key industry trends

Moving to inline contact resistance is critical for a number of reasons. First, systems-on-chip (SoCs) face a daunting roadmap for wafer probing, as Figure 1 indicates.

Figure 1. The International Technology Roadmap for Semiconductors (ITRS) spotlights significant challenges for wafer probing through 2020.
*International Technology Roadmap for Semiconductors 2015
**Full Wafer Contact

The data shown in the table for 2016 – 66,000 individual probes making contact with one die – was fairly conservative. Today, the industry is exceeding those numbers, which were published in 2015, by more than 150%. Every probe must be clean and accurate, and therein lies the challenge. Sometimes, the same die is being probed three to four times – perhaps at a different temperature each time – and each probe kicks up oxide “dirt.” In addition, dirt accumulates as the probe moves across the wafer (through the lot) since the same probe is used for each die on the wafer. It’s a problem of numbers, repeatability and trends for a series of wafers and a series of die.

Further complicating this, engineers are now doing more than final test at wafer probe, e.g., at-speed testing and Known-Good-Die (KGD) testing. Getting to KGD is, of course, the ultimate goal – they want to touch down on the die and know that everything works before packaging. This is not easy to achieve. More types of testing, such as high- and low-temperature tests, must be performed – all of which will be challenged by poor contact resistance.

Moving to contact resistance measurements is also critical because of the need to accommodate probe planarity issues. In the environment of the ATE, the probe needs to be held in as planar a manner as possible while, at the same time, a force of 200kg or more is pushing down on the probes. This pressure will cause the probe assembly to bow, making true planarity difficult to maintain. The probe micrograph in Figure 2 provides an example of this problem. The contact resistance in the center of the die was much higher than at the periphery, and much lower at the southern edge. The culprit: bowing up in the center of the die, which created a balloon effect that caused the center and part of the northeast portion to be bad. While a reading of anything less than 8 ohms is considered acceptable, high-power probing requires less than 4 ohms, making Cres requirements much tighter in high-power and extreme-temperature environments.

Figure 2. This example contact resistance (Cres) plot clearly shows bowing in the center of the probe.

Contact resistance measurement process

The diagram in Figure 3 represents circuits typically found in a variety of devices, each of which can benefit from inline Cres measurement. While many readers will be familiar with these diagrams, here is a brief summary of each type: 3a is a traditional I/O circuit with two diodes, one connected to a power supply and one to ground; 3b is similar, with a resistor added to each diode in series; 3c consists of one large diode with a resistor in series; 3d contains a single diode going to ground only and not a power supply; 3e is the opposite, with the diode going to the power supply and not to ground; and 3f represents the class of interfaces known as SerDes, used in high-speed communication. These circuits are unknowns in many respects – they are very different from any other type of circuit and by far the most difficult to assess for contact resistance.

Figure 3. Each type of circuit illustrated in this black box diagram can benefit from inline Cres measurement.

Inline contact resistance measurements can be performed in a variety of ways. Using standard digital pin parametric measurement unit (PPMU) resources enables tracking changes to contact resistance – either over time or positionally. To measure the contact resistance of I/O pins, the engineer basically forces currents, measures voltages, and then performs calculations to determine Cres.

Conceptually, Cres is calculated using this equation:

*************

can be calculated by looking at the diode equation:

**************

Which can be reordered to calculate the change in diode voltage:

The challenge with this equation is what value to use for diode ideality η. This value is not a constant, it varies with technology, process, and transistor geometry. All the other values are known, e.g., q = transistor charge, k = Boltzmann constant, T = die temperature, etc. Because, as noted above, different device pins have different (or no) diodes, the diode configuration becomes critical when trying to determine the value of η. Since diodes may exist to ground, supply, or both, either positive currents/voltage or negative currents/voltage may need to be used in order to obtain valid Cres measurements.

The curves for each pin type also need to be individually analyzed to solve for diode ideality η. Once determined, ideality values don’t seem to change for a given process and design. However, ideality values can vary broadly – the pins shown on the graph in Figure 4 have idealities between +60 and -2.6. Many different pins are superimposed on top of each other, all showing very different performance. The key point to note here is that, when the correct value is determined for η, Cres doesn’t change with different current levels.

Figure 4. By looking at this plot, the test engineer can determine which type of ESD protection circuit is being employed, and use portions of the plot to calculate η.

 

Determining values for η

The process for determining η involves the following steps:

  1. Force different currents into and out of all DUT pins and measure the voltage. For the purpose of this article, the currents selected were ±20mA, ±10mA, ±5mA, ±2mA, ±1mA and ±0.5mA.
  2. Select three positive or three negative measurements, and calculate ideality using this formula:
  3. Try different current values in the equation to check if the ideality stays relatively constant. With the right value for η the result will change very little. Also, all pins with a similar I/O buffer design will have the same η value.
  4. Perform a final check of the ideality selected by using the value in the Cres equation. The resistance value should be positive and will not change with different current levels.

At this point, production measurements of Cres can be performed by simply performing two current force and voltage measurements (of the same polarity that was used for calculating Image) and then performing the following calculation for Cres:

Example Cres measurement results are shown in Figure 5. Measurements were taken at two different force levels (140 lbs. and 92 lbs.), and on a pin-by-pin basis, Cres rose by about 2 ohms between them. The orange plot at 69 ohms highlights a failure in the making. Cres should be lower with higher force, so this tells us that the contactor bowed.

Figure 5. This graph provides the distribution of measurement results obtained at two different overdrive levels. Pins with resistors in series with their ESD diode are clearly visible at ~ 33Ω. Those without are at ~9Ω.

Determining Cres of SerDes pins

SerDes pins are difficult to analyze. They often have, pre-emphasis and equalization circuits on the inputs and outputs to match the on-die circuitry to their transmission lines. This greatly complicates conducting Cres measurement on these pins.

Figure 6. Changes in termination resistance values can help determine Cres for SerDes pins.

As seen in Figure 6, on part of the I-V curve, the slope of lines is about 100 ohms, as SerDes pins typically have termination resistors of 100 ohms, so the I-V curve will show this resistance, not Cres. The good news is that these termination resistance values do change with Cres changes – so the engineer can measure nominally 100 ohms using traditional Ohm’s law equations without the diode voltage adjustment, and then watch to see if the measurement value increase as the Cres degrades.

The test methods described so far are all two-terminal inline test methods. It’s important to recognize that two-terminal measurements will inherently include additional resistances in addition to the key Cres value to be determined. This is shown in Figure 7.

Figure 7. Two-terminal contact resistance stray values are compensated for over time.

While the test system is designed to compensate for all the resistances in the grey fields, it cannot compensate for the green resistors. As a consequence, the Cres values measured by these techniques will 1) be higher than normally expected, and 2) vary from pin to pin due to fixture design differences. The best way to deal with this situation is to simply save a baseline set of Cres as measured by these two-terminal techniques and then monitor the difference between the baseline and the Cres values measured over time.

Determining Cres of supply pins

A supply’s contact resistance can also be measured using a PPMU and a device power supply (DPS) monitor pin. In connecting the DPS in the test system to the DUT pins, it is becoming common practice to connect one of the DUT supply pins to a digital PMU pin. In addition to providing an enhanced ability to monitor the on-die supply voltage, this approach allows direct measurement of Cres from the digital pin to the DPS signal itself, and thus, direct calculation of the contact resistance average value for the DPS interconnection. Using the monitor pin, a simple I-V curve is observed (Figure 8) which allows straightforward calculation of the Cres. Complicating this for high-power designs is the very large number of supply pins in parallel. While this technique will still measure the average contact resistance it is less sensitive to changes in Cres at the per-pin level.

Figure 8. I-V curve for supply-pin Cres measurement. The sensitivity of this measurement to single-pin Cres issues drops as a large number of probes are connected in parallel.

Determining Cres of ground pins

This designed-in capability is unique to Advantest. In power-supply modules, a current is forced through a primary path, and then another path is used to sense voltage-out on the device under test (DUT) board. One of the available modules for the V93000 test system is called the UHC4. The UHC4 has a contact resistance monitor circuit built directly into the supply, giving it the unique ability to measure the voltage difference between force and sense right in the instrument (Figure 9).

Measuring a low value of resistance requires a high current (i.e., measurements must be taken during a power-up condition). As a simple example: with the part in an active mode, consuming, say 100 amps, a 1-volt change across the pins tells the user that all resistors are exhibiting 10 milliohms of resistance. A shift in the resistance indicates a ground connection problem. Continually monitoring the module will provide a good level of sensitivity to any big issues that arise.

Figure 9. The V93000 UHC4 module is uniquely able to measure voltage difference between force and sense.

High-accuracy Cres measurement

Using the precision DC measurement resources available in the V93000, high-accuracy Cres measurements can be made using thermal measurement diodes with four-terminal techniques. Several resources can be used to make these measurements. The results of a Monte-Carlo analysis of the measurement Imageaccuracy with the available instruments are provided in the table at right, which clearly shows the benefits afforded by Advantest’s DC-scale AVI64 universal analog pin module over the per-pin PMU of the PS1600.

In summary

The Advantest V93000 is able to measure both inline (2-terminal) and high-accuracy (4-terminal) contact resistance. These measurements will become more critical as the industry moves to higher pin counts, higher power levels and lower voltages. Expanded testing at the wafer probe will also drive this trend, as will extreme-temperature testing, which makes everything more difficult.

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